SoC 白盒IP设计

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Oct 16 -18

Compositor IP

概述特征请求数据表

Description

The compositor sets-up display priorities and mixes real time SD, HD or Quad HD video planes from display processors and memory Flexible IP, configurable as per SoC need Made of one or several MIXER (HW composer) and GDP (versatile Graphics data DMA and processing) Available From 2.25 mm2 (Ultra HD 4K) to 0.46 mm2 (Full HD 2K)

composistor

Features

  • Flexible IP, configurable as per SoC need • Made of one or several MIXER (HW composer) and GDP (versatile Graphics data DMA and processing)
  • Next 4K mandatory features – HDR,2 pixels per clock cycle on GDP+, Capture 10b (same as DVP IP)
  • AXI4 migration
  • Quad HD compositor up to 4 mixers
  • The output color format is RGBsigned – up to 3 video layers & up to 8 GDP layers
  • The output color format is RGBsigned – up to 2 alpha plans & up to 2 capture pipelines
  • Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers
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