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May 23 - 24 Shenzhen

DVB T2 Modulator CMS0041 IP



The Commsonic CMS0041 DVB-T2 Modulator provides all the necessary processing steps to modulate single transport stream into a complex I/Q signal for input to a pair of DACs, or interpolating DAC devices such as the AD9857/AD9957 or RF- DACs such as the AD9789. Optionally the output can be selected as an IF to supply a single DAC.

Additional extension cores are available for multiple- PLP (common/data) support, T2MI interface support and SFN deployment support.

The design has been optimized to provide excellent performance in low cost FPGA devices such as the Cycloneä range from Altera or the Spartan range from Xilinx

Processing Steps are following -:

  • TS Processing
  • Null packet deletion
  • CRC-8 Encoding
  • Baseband buffer and Padding
  • Baseband Scrambling
  • BCH, LDPC Encoders
  • Bit Interleaver and Demux
  • Mapping and Rotation
  • Cell and Timing Interleaving
  • T2 Frame builder
  • Frequency interleaving and Pilot insertion
  • IFFT
  • Resampler
  • Baseband-to-IF
  • DAC Aperture Correction
  • Radio Interface
  • Register Bank


  • Compliant with ETSI EN 302 755 including T2-Lite.
  • Enables rapid development of audio/visual systems using commodity Free-to-Air set-top-box technology and low-cost FPGAs.
  • Configurable support for 1K, 2K, 4K, 8K, 16K and 32K OFDM modes.
  • Integrated LDPC channel coder with short (16kb) or normal (64kb) frame support.
  • Automatic L1-PRE/L1-POST padding and puncturing.
  • Configurable support for 1/4, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 1/3 and 2/5 code-rates.
  • BPSK, QPSK, 16-QAM, 64-QAM and 256-QAM support.
  • All pilot patterns supported : PP1…PP8
  • SISO and/or MISO operation.
  • Future Extension Frames (FEF) support.
  • Optional L1-ACE and P2 bias cells processing.
  • Optional CPU-free configuration.
  • Optional Cell-ID, Network-ID and T2-System-ID local insertion.
  • Variable channel bandwidth support using a single clock reference; 1·7MHz… 10MHz.
  • AD9857/AD9957/AD9789 interface and auto-programming support.
  • AD9516/ADF4350 PLL programming support.
  • Extension core available for TS Adaptation featuring normal-mode or HEM operation with SPI/ASI interface and integrated PCR TS re-stamping.
  • Extension core available for T2MI interface support.
  • Extension core available for multiple-PLP support.
  • Extension core available for SFN support.
  • Extension core available for PAPR-TR support.
  • Seamless integration with Altera ASI megacore when using SPI/ASI extension core.
  • Optional FFT output windowing and/or in-band pre-distortion.
  • Optional dual-clock architecture for increased flexibility.
  • Designed for very efficient FPGA implementation without compromise to the targeting of gate array or standard cell structures.
  • Supplied as a protected bitstream or netlist (Megacore for Altera FPGA targets).

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