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Nov 13-16 Munich

HDMI V1.4 Rx PHY IP

概述特征请求数据表

Description

HDMI receiver PHY (Physical layer) is a single-port IP core which is fully compliant with HDMI 1.4 specification. This HDMI RX PHY supports from 25MHz to 225MHz TMDS clock, and offers a simple implementation for system LSI for consumer electronics like HDTV. The HDMI receiver PHY performs most efficiently with HMDI receiver link IP core.

It is Silicon Proven in many Fab/Nodes including: 130/90/65/55/45/40nm.


Features

  • HDMI version 1.4 compliant receiver
  • Supports DTV from 480i to 1080i/p HD resolution
  • Supports 24bit, 30bit and 36bit color depth per pixel
  • Integrated cable terminator
  • Adaptive equalizer for cable
  • Adjustable analog characteristics
  • PLL band width
  • VCO gain
  • BGR voltage
  • Cable terminator resistance value
  • DLL digital filter characteristics
  • Integrated Audio PLL
  • 3.3V/2.5V/1.0V power supply
  • GLOBAL FOUNDRIES 65nm (C65G) process
  • Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results
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T2M提供高质量的已验证IP,包括各种模拟/混合信号,RF,数字和SW系统的解决方案。可用于通信,消费类电子和计算机产品的关键组成部分,包括IoT系统,可穿戴设备,蜂窝电话,平板电脑,M2M,RCU,机顶盒,电视机,DVD播放器和PC芯片组。 无论是fab工厂的工艺 /节点的移植还是特定的系统功能,T2M所提供的IP可以进行设计定制化修改以适合客户的具体要求。