SoC 白盒IP设计

LTE Cat0 1 UE Modem IP

概述特征请求数据表

Description

The design interfaces to an external Analog to Digital converter, which receives the analog signal from the external RF tuner. The included frequency correction can compensate for 500KHz frequency offsets for up to 20MHz channel bandwidth. The timing correction can correct mismatches as large as 50ppm.

The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to control its operation, and can be configured by an external processor via the AXI interface.

Features

  • LTE, Release 9 compliant CAT 0/1 PHY
  • Supports IF input
  • Flexible channel BW (1.4, 3, 5, 10, 15, 20) MHz
  • Modulation (QPSK, 16QAM, 64QAM)
  • PUSCH transmission:
  • Frequency hopping (Type 1, Type 2)
  • Data and control multiplexing (UL-SCH alone, UL-SCH multiplexed with UCI, UCI alone)
  • UCI (CQI, PMI, RI, ACK/NACK)
  • PUCCH transmission:
  • Format 1, Format 1a, Format 1b, Format 2, Format 2a, Format 2b
  • ACK/NACK
  • Random Access Preamble (Format 0, Format 1, Format 2, Format 3)
  • UL RS (PUSCH, PUCCH)
  • UL SRS (Transmission and hopping procedures for UL SRS in normal subframe)
  • CP length (Normal, Extended)
  • Primary Sequence Synchronization PSS (Primary Cell ID detection and initial timing synchronization)
  • Secondary Sequence Synchronization SSS (Secondary Cell ID detection and subframe synchronization)
  • CP Type detection (Normal, Extended)
  • PDCCH reception:
  • Blind decoding of PDCCH (UE specific search space, Common search space)
  • DCI parsing (all formats)
  • Monitored RNTI’s on PDCCH (All)
  • PDSCH reception:
  • TM 1 (Single antenna port 0)
  • DL RB allocation (Type 0, Type 1, Type 2 localized)
  • HARQ (supported)
  • Channel Estimation (Ver. 0) Flat fading only
  • Time tracking
  • Frequency tracking
  • Measurements (supported)
  • Parallel and Serial outputs
  • Register File port (Slave) to external processor
  • Applications

  • Machine to Machine communications
  • Wireless sensor networks
  • Deliverables

  • Synthesizable Verilog
  • System Model (Matlab) and documentation
  • Verilog Test Benches
  • Documentation
  • FPGA testing environment

请填写下方的表格

T2M提供高质量的已验证IP,包括各种模拟/混合信号,RF,数字和SW系统的解决方案。可用于通信,消费类电子和计算机产品的关键组成部分,包括IoT系统,可穿戴设备,蜂窝电话,平板电脑,M2M,RCU,机顶盒,电视机,DVD播放器和PC芯片组。 无论是fab工厂的工艺 /节点的移植还是特定的系统功能,T2M所提供的IP可以进行设计定制化修改以适合客户的具体要求。