SoC 白盒IP设计

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Sep 18 -19

LTE Cat0 1 UE Modem IP



The design interfaces to an external Analog to Digital converter, which receives the analog signal from the external RF tuner. The included frequency correction can compensate for 500KHz frequency offsets for up to 20MHz channel bandwidth. The timing correction can correct mismatches as large as 50ppm.

The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to control its operation, and can be configured by an external processor via the AXI interface.


  • LTE, Release 9 compliant CAT 0/1 PHY
  • Supports IF input
  • Flexible channel BW (1.4, 3, 5, 10, 15, 20) MHz
  • Modulation (QPSK, 16QAM, 64QAM)
  • PUSCH transmission:

  • Frequency hopping (Type 1, Type 2)
  • Data and control multiplexing (UL-SCH alone, UL-SCH multiplexed with UCI, UCI alone)
  • PUCCH transmission:

  • Format 1, Format 1a, Format 1b, Format 2, Format 2a, Format 2b
  • Random Access Preamble (Format 0, Format 1, Format 2, Format 3)
  • UL SRS (Transmission and hopping procedures for UL SRS in normal subframe)
  • CP length (Normal, Extended)
  • Primary Sequence Synchronization PSS (Primary Cell ID detection and initial timing synchronization)
  • Secondary Sequence Synchronization SSS (Secondary Cell ID detection and subframe synchronization)
  • CP Type detection (Normal, Extended)
  • PDCCH reception:

  • Blind decoding of PDCCH (UE specific search space, Common search space)
  • DCI parsing (all formats)
  • Monitored RNTI’s on PDCCH (All)
  • PDSCH reception:

  • TM 1 (Single antenna port 0)
  • DL RB allocation (Type 0, Type 1, Type 2 localized)
  • HARQ (supported)
  • Channel Estimation (Ver. 0) Flat fading only
  • Time tracking
  • Frequency tracking
  • Measurements (supported)
  • Parallel and Serial outputs
  • Register File port (Slave) to external processor
  • Applications

  • Machine to Machine communications
  • Wireless sensor networks
  • Deliverables

  • Synthesizable Verilog
  • System Model (Matlab) and documentation
  • Verilog Test Benches
  • Documentation
  • FPGA testing environment

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