SoC 白盒IP设计

Visit us at MWC

Feb 25 - 28 Barcelona




The D-PHY is a complete PHY, silicon-proven at multiple foundries. The D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI), Display Serial Interface (DSI) and Unified Protocol (UniPro) using the PHY Protocol Interface (PPI).

MIPI D_PHY adheres to MIPI D-PHY Specification. The MIPI D-PHY along with MIPI CSI Transmitter or CSI Receiver or DSI Host or DSI Slave provides a complete solution for encoding or decoding MIPI data.


  • Compliant with MIPI D-PHY Spec v0.9
  • Programmable 1, 2 or 4 Data Lane Configuration.
  • Supports High-Speed and Low-Power modes.
  • Operate in continuous and non-continuous clock modes.
  • Data Rate: 800 Mbps per lane on silicon (Spec mentions a max of 500 Mbps per lane) in HighSpeed mode and 10Mbps in Low-Power mode.
  • Benefits

  • Highly modular design
  • Fully synchronous design
  • Active low Asynchronous reset
  • Applications

  • Verilog HDL
  • FPGA: Xilinx ISE on Virtex 5
  • Modelsim
  • Deliverables

  • RTL code
  • Detailed design document
  • Verification environment
  • Test cases
  • Synthesis environment/scripts
  • Tech Specs

  • MIPI D Phy

T2M提供高质量的已验证IP,包括各种模拟/混合信号,RF,数字和SW系统的解决方案。可用于通信,消费类电子和计算机产品的关键组成部分,包括IoT系统,可穿戴设备,蜂窝电话,平板电脑,M2M,RCU,机顶盒,电视机,DVD播放器和PC芯片组。 无论是fab工厂的工艺 /节点的移植还是特定的系统功能,T2M所提供的IP可以进行设计定制化修改以适合客户的具体要求。