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Nov 13-16 Munich

MIPI DigRF v4 IP

概述特征请求数据表

Description

The DigRF – Version 4 (DigRF v4) interface is a high-speed serial interface technology with high bandwidth capabilities, which was developed specifically for a wide range of emerging mobile applications.
DigRF provides the mobile industry a standard, high speed interface for mobile communication involving various technologies like 2G,3G and other LTE standards.
The DigRF v4 implementation is intended for galvanic point-to-point connections consisting of a single, integrated Link between a handset Baseband IC (BBIC) and a radio transceiver (RFIC). The Base-band IC acts as the master to initiate the commands and data transfer to be sent out from the Antenna. The BBIC sets the desired operating configuration. It is also responsible for enabling the RFIC and to send the correct data/configuration. The Radio transceiver IC acts as slave to receive the commands and data from BBIC. It is configured by BBIC with necessary settings. RFIC sends the data and control information to antenna Interface.
MPHY acts as a communication medium between the BBIC and the RFIC. This layer receives/transmits data serially. It is expandable up to 4 data lanes which will increase the data transfer speed between BBIC and RFIC.


Features

  • Compliant with MIPI DigRF V4, MIPI M-PHY spec v2.0.
  • Lanes of each sub link (TX and RX) can be programmed separately up to 4 lanes.
  • M-PHY LS and HS data rates HS1X, HS2X supported.
  • Supports error handling and one level retry mechanism.
  • Supports Nested frame formats.
  • Supports 2G, 3G LTE standards.
  • Additionally Supports WiMax, EDGE/GSM, WCDMA technologies.
  • Supports ICLC commands for configuring in HS modes.
  • Configurable number of TAS frames.
  • Easy to integrate CPU type of interface for configuring registers.
  • Configurable I/Q formats.
  • ARQ management supported.
  • Supports HS-Burst dithering.
  • Supports all type of test modes like link test mode, loopback, clock testmode, etc.
  • Benefits

  • Highly modular design
  • Fully synchronous design
  • Configurable IP.
  • Deliverables

  • RTL code
  • Detailed design document
  • Verification environment
  • Test cases
  • Synthesis environment/script
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