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Sep 18 -19

MIPI M PHY IP

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Description

MIPI M-PHY is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, memory, power management and Baseband to RFIC.
MIPI M-PHY Type I physical layer, HS Gear3 and PWM Gear7 compliant, designed in CMOS 28 nm technology for use in devices of mobile platforms.
The following components are included: One transmitter (TX) and two receivers (RX) where:
The transmitter includes 8B/10B encoder, parallel to serial converter and line driver. Each receiver includes line receiver, clock, and data recovery circuit for re-synchronizing received data, serial to parallel converter and 8B/10B decoder. The PLL provides multiple phases of high speed clocks for use both in M-TX and M-RX. It is a ring oscillator and charge pump based PLL.
Compensation and Bangap provides compensation codes for resistor calibration in the lanes. It also provides the various voltage and current references for use in the various lanes.


Features

  • Input clock frequency: 19.2 MHz/26 MHz/38.4 MHz/52 MHz @ 1.8 V.
  • Refclk phase noise quality: integrated SSB phase noise of -66 dBc from 10 KHz to 10 MHz (noise assumed uniformly distributed in the entire band).
  • High Speed (HS) mode support upto Gear3 for both rate series (A and B), both for TX and RX. In HS mode, supports an intermediate bit rate of 3.952 Gbps (with 26 MHz refclk only).
  • PWM mode support upto Gear7, both for TX and RX.
  • Supports Sleep Mode, Hibernate Mode, Stall Mode and the various Burst states, that is,Type I state machine including the LINE-CFG states.
  • Supports terminated and unterminated operations.
  • Supports small amplitude and large amplitude.
  • Includes Built in PHY Test mode (combination of TX and RX) with loopback (digital loopback only).
  • Phy Protocol Interface is compliant to mipi_MPHY_specification_v1-4 with 40 bit/ 20 bit /10 bit inter face options.
  • Macrocell includes clock multiplication unit (PLL) for high speed clock generation.
  • Macrocell DFT control is IEEE-1500 compliant.
  • Silicon Proven in multiple Fabs/Nodes
  • Benefits

  • 28 nm CMOS technology
  • Includes 1 transmitter and 2 receivers
  • Input clock frequency: 19.2 MHz / 26 MHz /
  • 38.4 MHz / 52 MHz @ 1.8 V
  • Applications

  • Display
  • Camera
  • Audio & video
  • Memory
  • Power management and Baseband to RFIC
  • Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • GDSII ported to required process node
  • Physical Design scripts
  • Hardware simulation test bench with regression test suit
  • Comprehensive documentation and training
  • Tech Specs

  • 28 nm CMOS technology
  • Includes 1 transmitter and 2 receivers
  • Input clock frequency: 19.2 MHz / 26 MHz /
  • 38.4 MHz / 52 MHz @ 1.8 V
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