SoC 白盒IP设计

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Oct 16 -18

SLIC IP

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Description

This is a SLIC device specifically designed for wireless local loop (WLL) and ISDN terminal adaptors (ISDN-TA) and VoIP applications. One of the distinctive characteristic of this device is the ability to operate with a single supply voltage (from 5.5 V to 12 V) and self generate the negative battery by means of an on chip DC/DC converter controller that drives an external MOS switch.

The battery level is properly adjusted depending on the operating mode. A useful characteristic forthese applications is the integrated ringing GENERATOR.

The control interface is a parallel type with open drain output and 3.3 V logic levels. Constant current feed can be set from 20 mA to 40 mA. Off-hook detection threshold is programmable from 5 mA to 9 mA.

The metering pulses are generated on chip starting from two logic signals (0 and 3.3 V) one define the metering pulse frequency and the other the metering pulse duration. An on chip circuit then provides the proper shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed by external components. A dedicated cancellation circuit avoid possible codec input saturation due to metering pulse echo.


Features

  • Monochip subscriber line interface circuit (SLIC) optimised for WLL and VoIP applications
  • Implement all key features of the BORSHT function
  • Single supply (5.5 V to 12 V)
  • Built in DC/DC converter controller
  • Soft battery reversal with programmable transition time.
  • On-hook transmission.
  • Programmable off-hook detector threshold
  • Metering pulse generation and filter
  • Integrated ringing
  • Integrated ring trip
  • Parallel control interface (3.3 V logic level)
  • Programmable constant current feed
  • Surface mount package
  • Integrated thermal protection
  • Dual gain value option
  • BCD III S, 90 V technology
  • -40 to +85 °C operating range
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide
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