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SoC 白盒IP设计

USB 2.0 Super Speed host Controller IP

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Description

USB 2.0 Host controller is a highly configurable core and implements the USB 2.0 Host functionality that can be interfaced with third party USB 2.0 PHY’s. USB2.0 Host controller core is part of USB3.0 family of cores.
Host Controller core is architected with an high performance DMA engine based on xHCI specification. The core can be configured to support full-fledged USB 2.0 host controller based higher performance xHCI specification for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.
The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI,AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.
The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.
  • Configurable Options
  • Optional USB3.0 Core for Superspeed Support
  • Application Interface – AHB, AXI, PCIe
  • Configurable Buffer Sizes
  • xHCI Engine with configurable number of device slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc
  • Also available - USB 2.0 Audio , USB 2.0 HID,USB 2.0 OTG Controller and USB2.0 Device Controller and Device

Features

  • Compliant with xHCI Rev1.0
  • Compliant with USB Specification Rev 2.0
  • Supports HS/FS/LS mode of operation.
  • Asynchronous clocking between Host Controller and Application logic.
  • Supports Aggressive Low Power Management
  • Configurable PHY Interface: 8/16 UTMI, ULPI.
  • Flexible User Application Logic
  • Can be adapted by any SoC / OCBinterface / offchip interconnects – such asAHB, AXI, PCIe
  • Configurable Datawidth: 32, 64, 128 bit.
  • Simple Register Interface for internal Register Access.
  • Support for various Hardware and Software Configurability regarding Core characteristics.
  • Easy migration path for Superspeed Support
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Applications

  • Human Interface Devices like keyboards,
  • mousses or game peripherals
  • Mass Storage devices like flash disks, mp3 or mp4 players
  • GPS navigation systems
  • Digital Cameras
  • Cellular phones
  • Audio devices like microphones and speakers
  • Printers
  • Scanners
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support

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