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Nov 13-16 Munich

USB 3.0 SSIC Controller IP


The USB 3.0 SSIC controller is a highly configurable core and implements the USB 3.0 SSIC functionality that can be interfaced with third party M-PHY’s. USB3.0 SSIC controller core is part of USB3.0 family of cores.
The SSIC Controller core is architected to seamlessly integrate with either in-house developed SS Host/Device Controller cores or with standard 3rd party SS Host/Device Controller cores.

The SSIC Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.

The controller when integrated with in-house Device/xHCI Host controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.

The controller’s simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. This solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally.



  • Compliant with SSIC v1.01
  • Compliant with M-PHY Specification v2.0
  • Compliant with USB3.0 Pipe Specification
  • Supports Type I M-PHY Port
  • Supports 1/2/4 M-PHY Lanes
  • Supports PWM-G1, HS-G1/G2/G3 Rate A/B series
  • Implements PHY adapter which bridges between RMMI and USB 3.0 Pipe
  • Asynchronous clocking USB 3.0 Controller and RMMI Bridging Layer
  • Configurable USB 3.0 PIPE Interface: 8, 16, 32 bit
  • Configurable RMMI Interface width: 8, 16, 32-bit
  • Supports Aggressive Low Power Management
  • Can seamlessly integrate with 3rd Party USB 3.0 Host/Device Controller cores
  • Can integrate with in-house USB 3.0 Host/Device Controller to expose flexible User Application Logic
  • Can be adapted by any SoC / OCB interface / off chip interconnects – such as AHB, AXI, PCIe
  • Configurable Data width: 32, 64, 128 bit
  • Simple Register Interface for internal Register Access
  • Support for various Hardware and Software Configuration regarding Core characteristics


  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Multiple loop backs for debug


  • Design Guide
  • Verification Guide
  • Synthesis Guide

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