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Nov 13-16 Munich

USB 3.1 Device Controller IP

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Description

USB 3.1 Device controller is a highly configurable core and implements the USB 3.1 Device functionality that can be interfaced with third party USB 3.1 PHY’s. USB3.1 Device controller core is part of USB3.0 family of cores named “Pravega”.

The Pravega Device Controller core is architected with an high performance DMA engine based on USB3.1 specification.The Pravega Device Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.

The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.

The Controller also has a dedicated PHY Type-C connector Interface for identifying Type-C specific features such as cable orientation, ID function based on Configuration data channel etc.

Features

  • Compliant with USB3.1 Specification Rev1.0
  • Implements Phy Logical/ Link / Protocol Layers.
  • Supports Aggressive Low Power Management
  • Configurable system clock frequency
  • Support simultaneous Multiple IN transfers.
  • Implements PTM.
  • Supports Bulk Streaming.
  • Configurable PIPE Interface: 8, 16, 32 bit.
  • Flexible User Application Logic whichincludes Optional Support for EP0 Processer for processing control transfers
  • Optional proprietary DMA Controller in Application Layer.
  • Optional support for Type-C connectors
  • Supports Type2 Header Buffers
  • Supports SCD/LBPM LFPS Messages
  • Simple Register Interface for internal Register Access.
  • Support for various Hardware and Software Configurability regarding Core characteristics.
  • Support Data, Video and Switch
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Deliverables

  • Configurable RTL Code
  • Configurable synthesis shellz
  • Protocol checkers, bus watchers and performance monitors
  • Test cases
  • HDL based test bench and behavioral models
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