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CCM3 Core

OverviewFeaturesRequest Datasheet

Description

The AES core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. Basic core is very small (less than 3,000 gates). Enhanced versions are available that support encryption and decryption for various cipher modes (ECB, CBC, OFB, CFB, CTR), as well as different datapath widths for size/performance tradeoff. The core includes the key expansion logic.

The design is fully synchronous and available in both source and netlist form. Test bench includes vectors from FIPS-197 and the original Rijndael submission. AESAVS tests are also available. AES Core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

Optional data integrity and differential power attack resistance features.

The AES core is available in ECB, CFB, CBC, OFB and CTR modes, and for different datapath widths. Decryption option is also available.

Features

  • Encrypts using the AES Rijndael Block Cipher Algorithm
  • Satisfies Federal Information Processing
  • Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
  • Processes 128-bit data blocks with 8, 16, 32, 64 or 128-bit wide data interface
  • Employs key size of 128,192 and 256 bit.
  • Includes the key expansion function
  • Supports basic modes of AES defined in
  • SP800-38A: ECB, CBC, CFB, OFB and CTR
  • Completely self-contained: does not require external memory
  • Optional countermeasures against power attacks (SPA and DPA)
  • Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected result

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OverviewFeaturesRequest Datasheet

Description

AKW1 implements the NIST standard AES key wrap and unwrap. Core contains the base AES core AES1 and is available for immediate licensing.

The design is fully synchronous and available in both source and netlist form.

The core is designed for flow-through operation, with 8/16/32/64/128-bit wide input and output interfaces. AKW1 supports both encryption (wrap) and decryption (unwrap) modes.

Features

  • Small size: AKW1 starts from less than 8,000 ASIC gates
  • Completely self-contained: does not require external memory
  • Supports both encryption (wrap) and decryption (unwrap). Encryption-only and decryption only versions available.
  • Includes AES key expansion
  • 128 and 256 bit AES key encryption keys (KEK) supported.
  • Flow-through design
  • Test bench provided
  • Benefits

  • The core is designed with 8/16/32/64/128-bit wide input and output interfaces. AKW1 supports both encryption (wrap) and decryption (unwrap) modes.
  • Applications

  • AES key wrap per NIST key wrap specification and RFC 3394
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • User Documentation
  • Netlist Licenses

  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • Tech Specs

  • AES Key wrap

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OverviewFeaturesRequest Datasheet

Description

The KSM1 core implements Kasumi encryption in compliance with the ETSI SAGE specification. It processes 64-bit blocks using 128-bit key. The basic core is very small (5,500 gates). Enhanced versions are available that support various cipher modes (ECB, CBC, OFB, CFB, CTR).

The design is fully synchronous and available in both source and netlist form. Test bench includes the Kasumi test vectors. The KSM1 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

Features

  • Encryption using the Kasumi Block Cipher Algorithm
  • Since all practical uses of Kasumi utilize only the encryption operation, decryption is not part of the core
  • High throughput: up to 3 Gbps in 65 nm process
  • Small size: from 5.5K ASIC gates, 289 Xilinx slices, 617 Altera ALUTs
  • Satisfies ETSI SAGE Kasumi specification and 3GPP TS 35.202
  • Processes 64-bit data blocks
  • Use 128-bit key
  • Completely self-contained: does not require external memory
  • Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables include test benches

Benefits

  • Technology        Max Freq.       Area               Throughput
  • TSMC65 G+       168 MHz       5,448 gates       1.3 Gbps
  • TSMC65 G+       365 MHz       7,675 gates       2.9 Gbps
  • Xilinx Virtex 5     100 MHz       289 slices        800 Mbps
  • Altera Stratix 3   120 MHz       616 AL
  • UT 960 Mbps

Applications

  • Secure mobile phone communications
  • 3GPP UMTS algorithms f8 and f9
  • A5/3 implementation
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Test vectors
  • Expected results
  • User Documentation
  • Netlist Licenses

  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Test vectors
  • Expected results
  • Tech Specs
  • Kasumi Cipher<>

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OverviewFeaturesRequest Datasheet

Description

The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. The basic core is small (6,500 gates) and uses an external 256-bit entropy seed to generate 16 bytes (128 bits) of random data at a time (128 bits of security strength). Versions of the core are available supporting higher security strengths (192 and 256 bits), larger amounts of generated bits (up to 2^19 ), and different internal datapath widths for size/performance tradeoff. The core includes the AES1 core. The design is fully synchronous and available in both source and netlist form. Test bench uses vectors in plain text format. The PRNG1 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

Features

  • Generates cryptographically secure pseudo-random numbers
  • Uses the CTR_DRBG algorithm per NIST publication SP800-90
  • Generates 128-bit data blocks with 8, 16, 32, 64 or 128-bit wide data interface
  • Provides security strength of 128,192 and 256 bits
  • Self-contained; does not require external memory
  • Available as fully functional and synthesizable Verilog or VHDL, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables include Verilog test bench and test vectors
  • Benefits

  • Psuedo Random Generator
  • Applications

  • Secure wireless communications, including 802.11i, 802.15.3, 802.15.4 (ZigBee), MBOA, 802.16e
  • Electronic financial transactions
  • Content protection, digital rights management (DRM), set-top boxes
  • Secure RFID
  • Secure Smart Cards
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Testbench (self-checking)
  • Test vectors
  • Expected results
  • User Documentation
  • Netlist Licenses

  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Test vectors
  • Expected results
  • Tech Specs

  • Cryptographically Secure Pseudo Random number Generator IP Core

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OverviewFeaturesRequest Datasheet

Description

The SHA cores provide implementation of cryptographic hashes SHA-1 (core SHA1), SHA-2 (cores SHA2-256 and SHA2-512). The cores utilize “flow-through” design that can be easily included into the data path of a communication system or connected to a microprocessor: the core reads the data via the D input and outputs the hash result via its Q output. Data bus widths for both D and Q are parameterized. The design is fully synchronous and is available in both source and netlist form

Features

  • Completely self-contained; does not require external memory
  • SHA1 supports SHA-1 per FIPS 180-1, SHA2-256 and SHA2-512 support SHA-2 per FIPS 180-2.
  • HMAC option is available with flow-through and microprocessor-friendly (-SK) interfaces for the key input.
  • Flow-through design; flexible data bus width
  • Test bench provided
  • Benefits

  • SHA
  • Applications

  • Message digest calculation
  • Digital signature (DSA) algorithm of the Digital Signature Standard (DSS) per FIPS-186
  • Security protocols, including
  • TLS (RFC 2246, RFC 4346)
  • SSL v3
  • PGP (RFC 2440)
  • SSH (RFC 4251)
  • S/MIME (PKCS #7, RFC 3852)
  • IPSec (RFC 2404, RFC 4301)
  • Deliverables

    HDL Source Licenses

  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Test vectors
  • Expected results
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Test vectors
  • Expected results
  • Tech Specs
  • SHA

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OverviewFeaturesRequest Datasheet

Description

The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists of 32-bit blocks using 128-bit key and IV. The basic core is very small (7,500 gates). Enhanced versions are available that support UEA2 and UIA2 confidentiality an integrity algorithms. The design is fully synchronous and available in both source and netlist form. Test bench includes the ETSI/SAGE SNOW 3G test vectors. The SNOW3G1 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

Features

  • Keystream generation using the SNOW 3G Algorithm
  • High throughput: up to 7.5 Gbps in 65 nm process
  • Small size: from 7.5K ASIC gates
  • Satisfies ETSI SAGE SNOW 3G specification
  • Outputs keystream in 32-bit data blocks
  • Use 128-bit key and IV
  • Completely self-contained: does not require external memory
  • Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables include test benches
  • Benefits

  • SNOW 3G
  • Applications

  • Secure mobile communications
  • 3GPP Long Term Evolution (LTE) algorithms UEA2 and UIA2
  • ISO standard IS 18033-4
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Testbench (self-checking)
  • Test vectors
  • Expected results
  • User Documentation
  • Netlist Licenses

  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Test vectors
  • Expected result
  • Tech Specs

  • SNOW 3G

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OverviewFeaturesRequest Datasheet

Description

The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. It is compliant with FIPS 140-2 Annex C.The basic core is very small (8,000 gates) and contains the random seed source and a PRNG1 cryptographically secure pseudo-random generator core.The design is fully synchronous, with the exception of the seed part, and available in both source and netlist form. The core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security. The TRNG1 core is available in with different datapath widths and throughputs

Features

  • Satisfies Federal Information Processing Standard (FIPS) Publication 140-2 Annex C (“approved” random number generator) from the US National Institute of Standards and Technology (NIST). Passes the requirements of the NIST SP 800-22.
  • High security (128 bit entropy; 256 version available)
  • Initial seed provided from internal entropy source
  • Automatic re-seeding
  • High data rate
  • Completely self-contained: does not require external memory
  • Available as fully functional and synthesizable Verilog.
  • Deliverables include synthesis scripts
  • Benefits

  • Truly Random Generator
  • Applications

  • Secure wireless communications, including IEEE 802.16 WiMAX, 802.11 Wi-Fi WLAN, 802.15.3, 802.15.4 (ZigBee), MBOA, 802.16e
  • Electronic financial transactions, smart cards
  • Content protection, digital rights management (DRM), set-top boxes
  • Secure video surveillance systems
  • Military communication systems
  • Encrypted data storage
  • Secure RFID
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • Tech Specs

  • True Random Generator

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OverviewFeaturesRequest Datasheet

Description

The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3 version 1.6. It produces the keystream that consists of 32-bit blocks using 128-bit key and IV. Multiple configurations of ZUC1 core are available; the number after dash indicates the throughput in bits per clock, so ZUC1-32 version is 4 times faster than ZUC1-8. Enhanced –E3 version is available that supports both EEA3 and EIA3 confidentiality and integrity algorithms. Compact ZUC1-2-E3 core is very small (12K gates). The design is fully synchronous and available in both source and netlist form. Test bench includes the ETSI/SAGE test vectors.

Features

  • Keystream generation using the ZUC Algorithm version 1.6 (ZUC-2011)
  • High throughput: up to 40 Gbps in 65 nm process, 10 Gbps in Altera Stratix III
  • Small size: from 7.5K ASIC gates
  • Satisfies ETSI SAGE ZUC and EAE3/EIA3 specifications
  • Outputs keystream in 32-bit data blocks
  • Uses 128-bit key and IV
  • Completely self-contained: does not require external memory
  • Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables include test benches
  • Benefits

  • ZUC Cipher

    Applications

  • Secure mobile communications
  • 3GPP Confidentiality and Integrity Algorithm 128-EEA3 & 128-EIA3
  • Deliverables

    HDL Source Licenses

  • Synthesizable Verilog RTL source code
  • Software modules for a complete ECC implementation (optional)
  • Verilog testbench (self-checking)
  • Software modules test harness
  • Vectors for testbench and harness
  • Expected results
  • User Documentation
  • Netlist Licenses

  • Post-synthesis EDIF
  • Testbench (self-checking)
  • vectors for testbenches
  • Expected results
  • Tech Specs

  • ZUC Cipher

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OverviewFeaturesRequest Datasheet

Description

The CCM1 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C.

Specific protocol implementations are available in integrated cores:

  • WPA2 for IEEE 802.11i (Wi-Fi)
  • CCM3 for IEEE 802.15.3 (UWB)
  • CCM3M for MBOA
  • CCM6 for IEEE 802.16e (WiMAX)
  • CCMZ1/2 for IEEE 802.15.4 (Zigbee)

CCM1 core uses flow-trough design with dedicated inputs for key and nonce. Cores contain the base AES core AES1 and are available for immediate licensing. The design is fully synchronous and available in both source (Verilog or VHDL) and netlist form.

Features

  • From 10,000 ASIC gates for CCM1-8 configuration with 0.8 bits per clock throughput with 128-bit key
  • From 22,000 ASIC gates for CCM1-128 configuration with 12.8 bits per clock throughput with 128-bit key
  • Completely self-contained: does not require external memory
  • Supports encryption and decryption, Includes key expansion (scheduling)
  • Support for CCM mode of the AES cipher
  • Test bench provided
  • Benefits

  • The core can sustain the following peak throughput; depending on the configuration (performance is lower on shorter packets):
  • 0.8 to 12.8 bits per clock with a 128-bit key (e.g., 6.4 Gbps at 500 MHz clock)
  • 0.57 to 9.1 bits per clock with a 256-bit key (e.g. 4.5 Gbps at 500 MHz clock)
  • If higher throughput is required, use the CCM2 core, which if two times faster, yet is larger and has a lower maximum frequency.
  • Applications

  • Generic CCM-AES applications
  • IEEE 802.15.3 with 802.15.3 AES Core
  • IEEE 802.16e with 802.16e WiMAX AES Core
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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OverviewFeaturesRequest Datasheet

Description

The DES1 core implements DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard. It processes 64- bit blocks, with one, two, or three 56-bit keys. Basic core is very small (3,000 gates).

Enhanced versions are available that support various cipher modes (ECB, CBC, OFB, CFB, CTR. The design is fully synchronous and available in both source and netlist form. Test bench includes the NIST DES test vectors. DES1 Core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

A DES encryption operation transforms a 64-bit data block into a block of the same size. The encryption key size is 56 bits, with one to three keys used (one in single DES, two is double DES, and three in triple DES. If two keys are desirable in the 3DES EDE mode, the same key values shall be applied to K1 and K3 inputs of the core. The block performs DES encryption as defined by NIST in
FIPS 46-3.

Features

  • Encrypts and decrypts using the DES Block Cipher Algorithm
  • High throughput: up to 3 Gbps at 750 MHz in 90 nm LV technology
  • Small size: from 3K ASIC gates for a triple DES core
  • Satisfies FIPS 46-3 from the US National Institute of Standards and Technology (NIST)
  • Processes 64-bit data blocks
  • Employs one to three keys of 56 bits each
  • Completely self-contained: does not require external memory
  • Available as fully functional and synthesizable
  • Verilog, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables include test benches
  • Single-DES No License Required (NLR) option DES1-NLR
  • Applications

  • Secure mobile phone communications
  • Secure RFID
  • Secure Smart Cards
  • Secure financial transactions
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • User Documentation
  • Netlist Licenses

  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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OverviewFeaturesRequest Datasheet

Description

Implementation of the new LAN security standard 802.1ae (MACSec) requires the NIST standard AES cipher in the GCM mode for encryption and message authentication (AES-GCM). The GCM1 AES core is tuned for 802.1ae applications at the data rates of 1 Gbps and higher. The GCM2 family of cores is targeted towards high performance applications with high-end cores supporting data rates in excess of 100 Gbps and ability to parallelize to achieve even higher throughput. GCM3 is similar to GCM2, but supports AES key lengths up to 256 bits. For higher throughputs of 100 Gbps and above, use our GCM10 core family. Cores contain the base AES core AES1 and are available for immediate licensing. The design is fully synchronous and available in both source and netlist form.

Features

  • Small size: Starting at less than 13K ASIC gates, 1.5 Gbps performance at less than 20K gates
  • Scalability to throughputs of 128 bits per clock with the capability of parallel cores at throughputs of 100 Gbps and above
  • Supports Galois Counter Mode Encryption and authentication (GCM-AES a.k.a. AES-GCM)
  • Includes AES-GCM encryption, AES-GCM decryption, key expansion and data interface
  • Automatic generation of key context from key data and frame header
  • Flow-through design
  • Test bench provided
  • Optional NIST GCMVS algorithm validation
  • Deliverables include test benches
  • Benefits

  • The core is designed for flow-through operation, with 128-bit wide input and output interfaces.
  • Applications

  • WLAN IEEE 802.1ae MACSec
  • IEEE P1619.1 tape encryption
  • Fibre Channel Security Protocol FC-SP
  • IEEE 802.3ah (EPON) encryption
  • Deliverables

    HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • AES-GCM vectors for testbenches
  • Expected results
  • User Documentation
  • Optional GCMVS NIST validation
  • Netlist Licenses>
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • AES-GCM vectors for testbenches
  • Expected results
  • Place & Route script

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OverviewFeaturesRequest Datasheet

Description

LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption standard IEEE P1619 uses the XTS mode. Since GCM and XTS share some of their basic components, a combo GCM/XTS/CBC core is not much larger than a dedicated core for either of the modes.

The GXC3 core is tuned for mid-performance P1619 and 802.1ae applications at the data rates up to 10 Gbps. The core contains the base AES core AES1 and is available for immediate licensing.

The design is fully synchronous and available in both source and netlist form.

The GXC3 implementation fully supports the AES algorithm for 128 and 256 bit keys in Galois Counter Mode (AES-GCM) as required by the 802.1ae IEEE standard, in AES-XTS mode as required by the IEEE P1619 (SISWG) standard, a the CBC-AES mode per NIST specification SP800-38A.

The core is designed for flow-through operation, with input and output interfaces of flexible width. GCM additional authentication data precede the plaintext in the flow of data. GXC3 supports both encryption and decryption modes.

Features

  • Small size:
  • From 70K ASIC gates (at throughput of 18.2 bits per clock)
  • 500 MHz frequency in 90 nm process
  • Easily parallelizable to achieve higher throughputs
  • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
  • Support for Galois Counter Mode Encryption and authentication (GCM) , XEX-based Tweaked CodeBook mode (TCB) with Cipher Text Stealing (CTS) (abbreviated as XTS) mode per IEEE P1619, and Cipher Block Chaining (CBC) mode with 128 and 256-bit AES keys
  • Flow-through design
  • Test bench provided
  • Applications

  • IEEE 802.1ae
  • LAN switches, routers, NICs IEEE P1619
  • Hard drive and tape encryption, SAN, NAS
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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OverviewFeaturesRequest Datasheet

Description

LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption standard IEEE P1619 uses the XEX/XTS mode. Since GCM and XEX/XTS share some of their basic components, a combo GCM/XEX/XTS core is not much larger than a dedicated core for either of the modes. The GXM3 core is tuned for mid-performance P1619 and 802.1ae applications at the data rates of 2-3 Gbps and higher. The core contains the base AES core AES1 and is available for immediate licensing. The design is fully synchronous and available in both source and netlist form.

Features

  • Small size: From 60K ASIC gates (at throughput of 18.2 bits per clock)
  • 487 MHz frequency in 90 nm process
  • Easily parallelizable to achieve higher throughputs
  • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
  • Support for Galois Counter Mode Encryption and authentication (GCM) and XTS-AES mode per P1619
  • XEX-AES encryption mode
  • Cipher Text Stealing (CTS) included
  • Flow-through design
  • Test bench provided
  • Benefits

  • The GXM3 implementation fully supports the AES algorithm for 128 and 256 bit keys in Galois Counter Mode (GCM) as required by the 802.1ae IEEE standard and in XEX mode as required by the IEEE P1619 standard.
  • The core is designed for flow-through operation, with input and output interfaces of flexible width. GCM additional authentication data precede the plaintext in the flow of data. GXM3 supports both encryption and decryption modes.
  • Applications

  • IEEE 802.1ae: LAN switches, routers, NICs
  • IEEE P1619: hard drive and tape encryption, SAN, NAS
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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OverviewFeaturesRequest Datasheet

Description

LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption standard IEEE P1619 uses the XEX/XTS mode. Since GCM and XEX/XTS share some of their basic components, a combo GCM/XEX/XTS core is not much larger than a dedicated core for either of the modes. The GXM3 core is tuned for mid-performance P1619 and 802.1ae applications at the data rates of 2-3 Gbps and higher. The core contains the base AES core AES1 and is available for immediate licensing. The design is fully synchronous and available in both source and netlist form.

Features

  • Small size: From 60K ASIC gates (at throughput of 18.2 bits per clock)
  • 487 MHz frequency in 90 nm process
  • Easily parallelizable to achieve higher throughputs
  • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
  • Support for Galois Counter Mode Encryption and authentication (GCM) and XTS-AES mode per P1619
  • XEX-AES encryption mode
  • Cipher Text Stealing (CTS) included
  • Flow-through design
  • Test bench provided
  • Benefits

  • The GXM3 implementation fully supports the AES algorithm for 128 and 256 bit keys in Galois Counter Mode (GCM) as required by the 802.1ae IEEE standard and in XEX mode as required by the IEEE P1619 standard.
  • The core is designed for flow-through operation, with input and output interfaces of flexible width. GCM additional authentication data precede the plaintext in the flow of data. GXM3 supports both encryption and decryption modes.
  • Applications

  • IEEE 802.1ae: LAN switches, routers, NICs
  • IEEE P1619: hard drive and tape encryption, SAN, NAS
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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OverviewFeaturesRequest Datasheet

Description

Implementation of the new ITU G.9961 standard for home networking requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and message authentication. The CCMG AES core is tuned for G.hn applications at 3-4 Gbps data rates. The core contains the base AES core AES1 and is available for immediate licensing.

The design is fully synchronous and available in both source and netlist form.

Features

  • Small size:
  • From 27,700 ASIC gates at G.hn data speeds
  • Completely self-contained: does not require external memory
  • Includes encryption, decryption, key expansion and data interface
  • Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC)
  • Automatic generation of key context from key data in the datastream
  • Flow-through design
  • Test bench provided
  • Benefits

  • The CCMG implementation fully supports the AES algorithm for 128 bit keys in Counter Mode (CTR) method of encryption with CBC message integrity check as required by the CCMP protocol of the G.hn standard, The core is designed for flow-through operation, with configurable-width input and output interfaces (the peak core throughput is 12.8 bits per clock). CCMG operates on LCDU blocks. CCM key material precedes the frame in the flow of data. CCMG supports both encrypt and decrypt modes.
  • Applications

  • G.hn ITU G.9661 based application
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The CMAC1 core provides implementation of cryptographic hashes AES-CMAC per NIST SP 800-38B and AES-XCBC.

The cores utilize “flow-through” design that can be easily included into the data path of a communication system or connected to a microprocessor: the core reads the data via the D input, key from the K input and outputs the hash result via its Q output. Data bus widths for D, K, and Q are parameterized. The design is fully synchronous and is available in both source and netlist form.

The throughput of the core on long data packets depends on the core configuration and ranges
  • from 0.8 bit to 12.8 bits per clock for the 128-bit key
  • from 0.57 to 9.1 bits per clock for the 256-bit key
  • On short packets, performance is up to two times lower.

    CMAC2 provides two times the performance of CMAC1 at the expense of larger size and lower maximum frequency

    Features

    • Completely self-contained; does not require external memory
    • CMAC algorithm per NIST SP800-38B and RFC 4493, AES-XCBC per CBC MAC submissions to NIST and RFC 3566.
    • Supports 128, 192, and 256 bit AES keys.
    • Flow-through design; flexible data bus width.
    • Self-checking test bench provided
    • Benefits

    • The core is designed for flow-through operation, with I/O interface of parameterizable width. The input data can contain any number of bytes (data padding is performed inside the core). The output data is the 128-bit MAC value.
    • Applications

    • Message digest calculation
    • AES-CMAC-96
    • AES-XCBC-96
    • AES-CMAC-PRF-128
    • AES-XCBC-PRF-128
    • IPsec
    • TLS
    • Deliverables

    • HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • Expected results
    • User Documentation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    IEEE 802.15.4 is the low-power wireless standard that is used by ZigBee Alliance as a base of its ZigBee™ specification. It uses the CCM* mode of the AES cipher for encryption and message authentication. The CCMZ cores are tuned for low-power IEEE 802.15.4 applications.

    CCMZ1 core is slightly larger and uses flow-trough design with key and nonce in the data stream; CCMZ2 core has dedicated inputs for key and nonce. Cores contain the base AES core AES1 and are available for immediate licensing.

    The design is fully synchronous and available in both source and netlist form.

    The CCMZ implementation fully supports the AES algorithm for 128 bit keys in Counter Mode (CTR) method of encryption with CBC message integrity check of all sizes required by the CCM* protocol of the IEEE 802.15.4 standard.

    The core is designed for flow-through operation, with byte-wide input and output interfaces. For CCMZ1, CCM key and nonce material precede the frame in the flow of data. Both CCMZ1 and CCMZ2 support encrypt/decrypt modes and includes on-the-fly key expansion (scheduling).

    Features

    • Small size:
    • From 6,000 ASIC gates at IEEE 802.15.4 data speeds
    • Completely self-contained: does not require external memory
    • Supports encryption and decryption,
    • Includes key expansion (scheduling)
    • Support for CCM* mode of the AES cipher
    • Flow-through design with frame header parsing
    • Test bench provided
    • Applications

    • IEEE 802.15.4 (ZigBee)

      Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Implementation of the WLAN security standard (802.11i) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and message authentication with the CCMP protocol and RC4/”Michael” cipher for the TKIP. The WPA3 core is tuned for high data rate 802.11i applications (up to 2 Gbps for the CCMP protocol for 802.11n/802.11ac). The core contains the base AES core AES1, base RC4 core ARC4 and is available for immediate licensing.

    The WPA3 implementation fully supports the AES algorithm for 128 bit keys in Counter Mode (CTR) method of encryption with CBC message integrity check as required by the CCMP protocol of the 802.11i standard. The core also supports ARC4 cipher with “Michael” authentication for the TKIP protocol as defined by the 802.11i standard.

    The core is designed for flow-through operation (FIFO-like), with byte-wide input and output interfaces. The key and nonce information are stored in the local memory and automatically updated. PHY header precedes the packet in the data flow. Core performs all necessary per-packet calculations, parses and modifies the packet headers. The decryption results are indicated in the dataflow, including the replay protection.

    WPA3 supports encrypt and decrypt modes

    The design is fully synchronous and available in both source and netlist form.

    Also avilable AES WPA2-IP - The WPA2 AES core is tuned for 802.11i applications and as such requires much smaller gate count than a full implementation.The core contains the base AES core AES1 and is available for immediate licensing.

      Features

    • Small size:
    • 8,900 ASIC gates at 802.11a/g OFDM data speeds
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    • Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC)
    • Automatic generation of key context from key data
    • Flow-through design
    • Test bench provided
    • Deliverables include test benches
    • Applications

    • WLAN 802.11i
    • Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Implementation of the new WPAN security standard for MBOA MAC requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and message authentication. The CCM3M AES core is tuned for MBOA MAC applications and as such requires much smaller gate count than a full implementation. The core contains the base AES core AES1 and is available for immediate licensing.

    The CCM3M implementation fully supports the AES algorithm for 128 bit keys in Counter Mode (CTR) method of encryption with CBC message integrity check as required by the CCM protocol of the MBOA MAC. The core is designed for flow-through operation, with byte-wide input and output interfaces. CCM key and nonce material precedes the frame in the flow of data. CCM3M supports encrypt and decrypt modes.

    The design is fully synchronous and available in both source and netlist form.

    Features

    • Small size: From 9,500 ASIC gates at MBOA data speeds
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    • Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC)
    • Automatic generation of key context from key data
    • Flow-through design
    • Test bench provided

      Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part of the “Suite B” of cryptographic algorithms approved by the NSA. Since ECC requires fewer bits than RSA to achieve the same cipher strength, it is frequently used in embedded applications. The operations necessary for the ECC cannot be efficiently implemented on an embedded CPU, however, typically requiring hundreds of milliseconds of the CPU time for signature verification.

    ECC1 implements by far the most time-consuming operation of the ECC cryptography: so called “point multiplication” to enable low-power operation of the battery-powered devices. It also supports the “point verification” operation to simplify the system integration. The design is fully synchronous and available in multiple configurations varying in bus widths, set of elliptic curves supported and throughputM

    Features

    • ECC1 implementation is unencumbered by any patents
    • Small size: ECC1-163 requires less than 10K ASIC gates
    • High throughput for long life battery powered applications: 5,000 point multiplications per second in the 65 nm ASIC process
    • Support for the NIST ECC binary fields 2163, 2233, 2283, 2409, and 2571
    • Support for NIST prime curves P-192, P-224, P-256, P-384, or P-512
    • Microprocessor-friendly interface
    • Optional countermeasures against power attacks (SPA and DPA)
    • Test bench provided
    • Applications

    • Secure communications systems
    • RFID
    • Implantable medical devices
    • Digital Rights Management (DRM) for battery powered electronics
    • Elliptic Curve Diffie-Hellman (EC-DH) standard ANSI X9.63
    • Elliptic Curve Digital Signature Algorithm (EC-DSA) standard ANSI X9.62
    • Digital Signature Standard (DSS) FIPS-186
    • B and K elliptic curves (163, 233, 283, 409, 571 bits) defined by NIST
    • IEEE P1363 curves over binary fields GF(2m)
    • TLS implementations per RFC 4492
    • Cryptographic messaging per RFC 3278
    • Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Software modules for a complete ECC implementation (optional)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”.The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, however, typically requiring many seconds of the CPU time for signature verification.

    RSA2-E implements by far the most timeconsuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices. The design is fully synchronous and available in multiple configurations varying in bus widths, set of finite fields supported and throughput

    Features

    • Small size: RSA2-1E starts from less than 15K ASIC gates (size depends on the core configuration).
    • Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications.
    • Support for RSA binary fields of configurable bit sizes.
    • Microprocessor-friendly interface using external dedicated memory for arguments, results, and scratch storage.
    • An option to share the memory with the microprocessor is available.
    • Test bench provided.
    • Applications

    • Secure communications systems
    • Digital Rights Management (DRM) for battery powered electronics
    • Digital Signature using Reversible Public Key (rDSA) standard ANSI X9.31
    • Digital Signature Standard (DSS) FIPS-186
    • PKCS RSA cryptography per RFC 2347
    • High performance RSA accelerators
    • Deliverable

    • HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. LXP2 implements the lossless compression /decompression algorithm and AES-XTS encryption /decryption on units of data (“blocks”).

    Typical applications include enterprise data storage.

    The design is fully synchronous and available in multiple configurations varying in bus widths and throughput.

    LXP2 delivers 1-3 Gbps of throughput in both FPGA and ASIC implementations. The compression ratio greatly depends on the data and somewhat depends on the frames size; on typical file corpuses varies between 1.5 and 2.

    Features

    • Each frame is compressed and decompressed independently
    • Compatibility with public-domain LZ software implementations allows for interoperability
    • Parameterizable maximum block size (up to 16 megabytes)
    • Support for compression and decompression in a single core; dedicates compression and decompression versions are available
    • Back-to-back compression with no gaps between the frames
    • Applications

    • High-performance solid-state storage
    • Disk and tape storage systems
    • Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. Lossless compression is used when it is important that the original and the decompressed data be identical, or when no assumption can be made on whether certain deviation is uncritical. Typical applications include data storage and transmission.

    LZR1 implements the lossless compression algorithm on short units of data (“frames”). The core supports frame sizes up to 4096 bytes.

    The design is fully synchronous and available in multiple configurations varying in bus widths and throughput.

    LZR1-6 can easily deliver 10 Gbps of throughput in both FPGA and ASIC implementations. The compression ratio greatly depends on the data and somewhat depends on the frames size; on typical file corpuses varies between 1.5 and 2.

    Features

    • Each frame is compressed and decompressed independently
    • High throughput: LZR1 easily scales to 10 Gbps in FPGA
    • Compatibility with public-domain LZ software implementations allows for interoperability
    • Support for compression and decompression in a single core; dedicates compression and decompression versions are available
    • Back-to-back compression with no gaps between the frames
    • Applications

    • Disk and tape storage systems
    • High-performance solid-state storage
    • Networking, including cellular backhaul
    • Deliverables

    • HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses

    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 802.3bj (100G Backplane Ethernet) standard draft for 100GBASE-CR4 and 100GBASE-KR4 PHY. The encoder and decoder functions are completely independent and packaged as two sub-cores, RS100-160E and RS100-160D respectively. Decoder corrects up to 7 word errors; an option supporting RS(544, 514) for 100GBASE-KP4 PHY (correcting up to 15 errors) is also available . The RS100-160E core implements the FEC encoder per section 91.4.2.9 of the IEEE 802.3bj draft standard. The core accepts sixteen 10-bit words (160 bit total) on every clock and outputs the encoded result 10 clocks later. The RS100-160D core implements the FEC decoder per section 91.4.3.3 of the IEEE 802.3bj standard. It accepts sixteen 10-bit words (160 bit total) on every clock and outputs the decoded result 51 clocks later. Versions with lower latency are available.

    Features

    Implements FEC Sublayer for 100GBASE-CR4 and 100GBASE-KR4 PHY (clause 91 of the IEEE 802.3bj standard) 100G Ethernet MAC-friendly interface. Core features include 160-bit parallel interface Almost self-contained, requires a small external RAM is available. A larger version without external RAM is available. Flow-through design; low latency.

    Deliverables

    HDL Source Licenses Synthesizable Verilog RTL source code Verilog testbench (self-checking) Vectors for testbench User Documentation Netlist Licenses Post-synthesis EDIF Testbench (self-checking) Vectors for testbench Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encoding schemes used in the ITU G.9960 standard. The decoder design is fully synchronous on a single input system clock. LDPC decoder uses offset min-sum layered belief propagation technique and was designed using sequentially-concurrent architecture. In order to detect that the correct codeword is found, set of tests are performed in early stop detection unit after finishing each iteration. The core contains input and output buffer to ease integration into user system . The Data Input Interface accepts a set of channel observation data in the form of quantized Log-Likelihood on coded bits (bit-LLRs). The Data Output Interface yields the results in the form of hard decision bits.

    Features

    • parameterized input data width 5-8 bit
    • parameterized internal data width 7-12 bit
    • nearly floating point performance with quantization of 6 input bits and internal computation in 10 bits (less than 0.3 dB from floating point BP with 50 iterations); early stop detection unit ;
    • bit-LLR input
    • Decoder throughput with 10 iterations at 400 MHz
    • clock frequency is listed in the Table 1 below
    • Decoder area:
    • 240K gates
    • 224 DPRAM 128x16
    • 128 DPRAM 32x16
    • 48 ROM 16x64
    • Encoder area:
    • 40K gates
    • 40 Kbit DPRAM
    • 50 Kbit ROM
    • Benefits

    • Technology Independent
    • Fully Synchronous Design
    • Highly Modular Design with clearly defined interfaces
    • Scan friendly RTL
    • Deliverables

    • RTL Verilog source code or synthesized netlist;
    • Full Verilog Test environment (Selfchecking);
    • Fixed point MatLab models runningunder Windows or Linux OS for simulation and test patterns generation;
    • User guide and scripts.
    • Changes to the internal design to meet customer requirements are possible

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40 Gbps/100 Gbps operation). The encoder and decoder functions are completely independent and packaged as two sub-cores, CEC1-66/2112E and CEC1-66/2112D respectively. Decoder corrects a single burst error of upto 11 bits.

    Features

    • Small size
    • Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
    • 10G/40G/100G Ethernet MAC-friendly interface
    • Practically self-contained: requires only memory for one 2112-bit block in the decoder.
    • Flow-through design; low latency
    • Benefits

    • The CEC1-66/2112E core implements the FEC encoder per section 74 of the IEEE 802.3 standard.
    • The CEC1-66/2112D core implements the FEC decoder per section 74 of the IEEE 802.3 standard.
    • Applications

    • IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40 Gbps/100 Gbps operation)
    • Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • Expected results
    • User Documentation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol.

    The hardware components are fully synchronous and available as Verilog source. The software components are available in C language.

    HDCP software written in C (CPU subsystem is not included)

    Hardware accelerators
    • AES1-CTR-HDCP: AES encryption/decryption capable of handling the PES streams
    • RSA2: An RSA hardware accelerator (optional, high-end CPUs can use the software implementation)
    • TRNG1: A true random number generator (optional, if entropy bits are available in the design, a software implementation can be used)
    • SHA2-256: A Sha-256 hash accelerator (optional, most CPUs can use the software implementation)

    Features

    • Support for all HDCP configurations:
    • HDCP Transmitter (-TX)
    • HDCP Receiver (-RX)
    • HDCP Repeater (-RPT)
    • Implementation of the HDCP Authentication protocol:
    • Authentication and Key Exchange (AKE)
    • With Key Derivation
    • Locality Check
    • Session Key Exchange (SKE)
    • Authentication with Repeaters
    • Data encryption:
    • Utilizes HDCP Cipher (AES-128-CTR)
    • Includes the Link Synchronization
    • Transmitter and Receiver utilize the counter information in the PES Private Data
    • FIFO-like flow-through interface with flexible bit width; simple integration into the datapath.
    • Microprocessor-friendly interface for programmable I/O is optional
    • Applications

    • Digital rights management (DRM)
    • HDCP 2.0 implementations for generic wired and wireless interfaces
    • Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Source code for software
    • Verilog testbenches for hardware components (self-checking)
    • Vectors and expected results for testbenches
    • Hardware models for software verification
    • User Documentation

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Implementation of the IPsec security standard at high data rates requires the cryptographic processing acceleration. The ISP1-12.8 core is tuned for applications with the data rates of 1-6 Gbps (less for TripleDES). The design is fully synchronous and available in both source and netlist form.

    The ISP1 implementation supports the IPsec protocol acceleration for cryptographic algorithms.

    The core is designed for flow-through operation. ISP1 supports encryption and decryption modes (encrypt-only and decrypt-only options are available).

    Features

    • Support for IPv4 and IPv6 packets
    • Support for the ESP and AH protocols
    • Insertion / removal of headers and trailers; internal padding
    • Transport and tunnel modes of operation
    • Integrity Check Value (ICV) insertion and validation
    • Support for ESP encryption algorithms per RFC 4835:
    • NULL
    • AES-CBC (128- and 256-bit keys)
    • TripleDES-CBC
    • Support for ESP (and AH for –AH option) authentication algorithms per RFC 4835:
    • HMAC-SHA1-96
    • AES-XCBC-MAC-96
    • Additional cryptographic algorithms available upon request
    • Small size combined with high performance:
    • Starting at less than 120K ASIC gates plus external memory sufficient to hold one packet
    • Peak throughput of 12.8 bits per clock for 128-bit AES encryption (7.7 Gbps at 600 MHz), 9.1 bits per clock for 256-bit AES encryption (5.4 Gbps at 600 MHz)
    • FIFO-like interface with flexible bit width; simple integration into the datapath.
    • Supports encryption and decryption
    • Support for Galois Counter Mode Encryption and authentication (GCM), Galois Message Authentication (GMAC)
    • Flow-through design
    • Test bench provided
    • OpenSSL integration (integration with other packages upon request)
    • Uses an external connection context database
    • No internal connection information storage
    • External database shall provide the replay protection
    • No segmentation/reassembly support in the transport mode
    • Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • Expected Results
    • User Documentation
    • Source code for OpenSSL integration
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites.
    SSL1-AXI has a “lookaside” interface to the rest of system through two AXI interfaces:
    • AXI3/AXI4 slave for control
    • AXI3/AXI4 master for data transfer

    The data stream through the control interface contains processing commands. Each command consists a pointer to the descriptor in the system memory. Descriptor contains source, destination, encryption context, processing length, and status.

    The encryption context (keys, encryption state, etc.) as well as the packets are stored in the system memory attached to the AXI bus and are read and written via the master interface. The design is fully synchronous and is available in Verilog.

    Features

    • Throughput of 6-8 bits per clock (600-800 Mbps at 100 MHz)
    • Supports both encryption and decryption
    • Optional public-key RSA and ECC engines
    • Done signal for interrupting the CPU
    • Test bench provided

      Applications

    • Embedded SSL/TLS applications

      Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message authentication, as well as header parsing and formatting operations on the transmitted and received packets. The basic MSP1 core is tuned for applications with a single Security Association (SA) and data rated100 Mbps to1 Gbps. Other options of the MSP1 cores are available supporting multiple SAs and data rates up to 100 Gbps.

    The design is fully synchronous and available in both source and netlist form.

    Features

      Small size combined with high performance:
    • Starting at less than 30K ASIC gates
    • 2 Gbps performance at 250 MHz
    • Self-contained, does not require external memory Optional statistic counters Very low latency
    • 12 clocks input-to-output (48 ns at 250 MHz clock)
    • Back-to-back packet processing
    • 64 bytes shortest packet
    • Supports encryption and decryption
    • Provides MACsec header parsing and modification:
    • Insertion and removal of the SecTag including the packet number (PN) and an optional SCI
    • RX packet validation
    • Insertion, validation and removal of the ICV
    • Replay protection based on the PN windowing
    • Includes key storage, lookup, and expansion
    • Key is provided on the input pins
    • Option with internal key storage with associative lookup is available
    • Support for Galois Counter Mode Encryption and authentication (GCM), Galois Message Authentication (GMAC)
    • Flow-through design
    • Test bench provided
    • Sample software for 802.1X-2010 (a.k.a. 802.1af, KEYsec, 802.1x-REV) key agreement (MKA) is provided
    • Deliverables
    • include test benches and optional NIST algorithm validation
    • Applications

    • WLAN 802.1ae MACsec
    • RFC 4869
    • Deliverables

      HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Optional GCMVS NIST validation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    The FFT4096 core the FFT and IFFT computations for N input samples, where N can be any power of 2 between 32 and 4096 (32, 64, 128,...…4096), in hardware with very low latencies. The core also supports 2N-point real time samples to complex symmetric frequency samples FFT and N complex symmetric frequency samples to 2N time domain real samples IFF

    Features

    • Supports 32/64/128/256/512/1024/2048/4096 point complex FFT and IFFT and up to 8192 point real-to-complex and complex-to-real FFT and IFFT and can switch dynamically. The real-to-complex and complex-to-real FFT/IFFT does not require any additional memory.
    • Built-in bit reversal. Outputs in natural order
    • Supports reading output data in any order (read address)
    • Low Latency. Can be customized to improve latency vs. gate count
    • Throughput of 1 sample per clock
    • Parameterized bit widths and fixed-point option.
    • Test bench with fixed-point Matlab and optional C++ models
    • Available in ASIC and FPGA technologies
    • Minimal gate count implementation
    • Supports flushing and re-starting of the FFT operation instantly
    • Configurable bit width based on SQNR requirement for random inputs or for a specific stimuli pattern.
    • Customization for OFDM applications
    • Applications

    • DSL
    • Broadband over power lines
    • Digital Video Broadcasting (DVB)
    • Ethernet-over-coax
    • Other OFDM-based communications
    • Deliverables

    • Synthesizable Verilog RTL source code
    • Fixed-point Matlab model
    • Optional C++ bit accurate model
    • Simulation scripts
    • Self-checking Test environment
    • Test-bench
    • Test-vectors
    • Expected results
    • Synthesis scripts
    • User Documentation

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption standard IEEE P1619 uses the LRW mode. Since AES-GCM and AES-LRW share some of their basic components, a combo GCM-AES/LRW-AES core is not much larger than a dedicated core for either of the modes.

    The GLM1 core is tuned for mid-performance P1619 and 802.1ae applications at the data rates of 3-5 Gbps and higher. GLM2 is designed for higher throughput up to 10 Gbps. Both cores use identical external interface, contain the base AES core AES1 and are available for immediate licensing.

    GLM3 core is similar to GLM2, but its interface supports variable message length in the GCM mode.

    The design is fully synchronous and available in both source and netlist form.

    Features

    • Small size: from 31,000 ASIC gates for GLM1 from 58,000 ASIC gates for GLM2
    • 400 MHz frequency in 130 nm process GLM1 throughput is 12.8 bits per clock GLM2 throughput is 25.6 bits per clock
    • Easily parallelizable to achieve higher throughputs
    • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
    • Support for Galois Counter Mode Encryption and authentication (GCM-AES) and Liskov, Rivest, and Wagner Mode (LRW-AES)
    • Automatic generation of key context from key data and frame header
    • Flow-through design
    • Test bench provided
    • Applications

    • IEEE 802.1ae LAN switches, routers, NICs
    • IEEE P1619, P1619.1 Hard drive and tape encryption, SAN, NAS
    • Deliverables

    • HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses

    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Implementation of the new WPAN security standard (802.15.3) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) or encryption and message authentication. The CCM3 AES core is tuned for 802.15.3 applications and as such requires much smaller gate count than a full implementation. The core contains the base AES core AES1 and is available for immediate licensing.

    The design is fully synchronous and available in both source and netlist form.

    Features

    • Small size:
    • From 9,500 ASIC gates at 802.15.3 data speeds
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    • Support for Counter Mode Encryption (CTR)
    • operation and CCM extensions (Counter Mode with CBC MAC)
    • Automatic generation of key context from key data
    • Flow-through design
    • Test bench provided
    • Applications

    • IEEE 802.15.3
    • Deliverables

    • HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses

    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    The RC4 core implements the RC4 stream cipher in compliance with the ARC4 specification. It produces the keystream that consists of 8-bit words using a key with the length up to 256 bits. The design is fully synchronous and available in both source and netlist form.

    RC4 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

    Features

    • Keystream generation using the RC4 algorithm
    • Small size: from 20K ASIC gates
    • Satisfies the ARC4 specification
    • Capability to save and restore internal state using a data bus with parameterized width.
    • Outputs keystream in 8-bit data words
    • Uses a key of up to 256 bits
    • Completely self-contained: does not require external memory
    • Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
    • Deliverables include test benches
    • Applications

    • SSL/TLS accelerators
    • Deliverables

    • HDL Source Licenses
    • Synthesizable Verilog RTL source code
    • Verilog testbench (self-checking)
    • Vectors for testbench
    • User Documentation
    • Netlist Licenses
    • Post-synthesis EDIF
    • Testbench (self-checking)
    • Vectors for testbench
    • Expected results

    Please fill in the form below

    T2M's range of high quality pre-verified, analog/mixed-signal, RF, Digital and SW system solutions, are used as critical building blocks of communications, consumer and computer products including IoT, Wearables, cellular, tablet, M2M, RCU, set-top boxes, TVs, DVD players and PC chipsets. IPs can be modified to meet the customer's specific requirement be it fab/node porting or proprietary features.