JESD 204B IP Core
- Widest feature set available in market.
- Scrambling and de-scrambling Included.
- High performance transport layer support.
- Build in test functions
- Silicon proven
- Lint/CDC optimized
- UVM regression tested
- Interoperability tested with leading PHY/Serdes vendors
- Solid documentation including integration guide
- Easy to use RTL test environment
- Targeting any RTL implementation like ASICs, ASSPs and FPGAs.