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May 23 - 24 Shenzhen

MAC RMII 10/100 IP

概要フィーチャーデータシートをリクエスト

Description

Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII in cooperation with external PHY device enables network functionality in design. It is capable to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The Core is able to work with wide range of processors: 8, 16 and 32 bit data bus, either little or big endian byte order format. The DMAC-RMII provides static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in variety of process technologies. This Core strictly conforms to the IEEE 802.3 standard.

Features

  • Conforms to IEEE 802.3-2002 specification
  • Configurable width CPU interface with little or big endianess:
  • 8-bit
  • 16-bit
  • 32-bit
  • Simple interface allows easy connection to CPU
  • Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories
  • Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
  • Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers
  • Supports full and half duplex operation at 10 Mbps or 100 Mbps
  • CRC-32 algorithm:
  • calculates the FCS nibble at a time
  • automatic FCS generation and checking
  • able to capture frames with CRC errors if required
  • Dynamic PHY configuration by STA management interface
  • Early receive and transmit interrupts to increase data throughput
  • Programmable MAC address
  • Promiscuous mode support
  • Allows operation from a wide range of input bus clock frequencies
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking
  • No internal tri-states
  • Lite design, small gate count and fast operation
  • Scan test ready
  • Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Phone & email support
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