HDMI 2.0 TX PHY IP
The HDMI 2.0 Compliant Phy supports up to 18gbps bit rate and enables to 4Kx2K resolution at 60Hz frame rate. It receives three streams (3x6Gbps) of 10-bit transition minimized data as input along with synchronous TMDS clock. It serializes and transmits them in differential form over three channels. The clock is also transmitted along with the data as a differential signal according to the specifications laid out in the Chapter “Electrical Characteristics” of the HDMI Standard specification of the Transmitter.
This block consists of high speed serializer and output differential buffers along with the differential output pads and power supplies required by the block. The electrical layer can work over the TMDS clock range from 25MHz to 600MHz.
It can be customized process nodes from multiple foundries.
- Compliant with HDMI 2.0 specification
- Input clock (TMDS_CLK) from 10MHz to 600MHz range
- Supports upto 4K2K @ 60 Hz, 3D 1080p @60Hz
- Up to 18Gbps BitRate (3 X 6Gbps/Channel)
- Pre-emphasis can be programmed as per the Board/Package parasitic’s
- 1.8V+150mV (Analog Supply), 1.0V Digital Supply (0.85V to1.1V)
- Area and process: Under NDA
- Power On Consumption: 43.2mW (Typ Process, Typ Preemphasis at 6.0Gbps)
- IOs integrated in the Digital and custom digital can be tested
- At Speed BIST incorporated
- In-built PRBS for Electrical Testing
- HDMI/DP is the digital interface standard for connecting HD consumer electronics components.
- Detailed specification with All log files and signoff checklist
- Integration Guidelines ( Interface details, layout guidelines, power requirements)
- GDSII layout and Mapping file with LEF Abstract (Top level pin details, blockages and Boundary details)
- LVS compatible netlist for the LVS clean