SoC White Box IPs

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Oct 16 -18

DDR4 LP Phy IP

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Description

This is a member of the high-speed Memory Interface family. This combo PHY is suitable to work with DFI 3.1 compliant memory controller and JEDEC DRAM memories. The state-of-art DDR PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. The benefits of our highly integrated PHY solutions include straight forward integration, differentiated performance, simplified interoperability, and extensive built-in testability.

This minimizes risk with extensive pre -silicon verification/interoperability program, resulting in highly reliable products, which are manufacturable in leading CMOS processes.Our enterprise class PHY offers up to 4 chip-select with independent training on each of them. PHY handles all the complex timing relationship and electrical specification required for successful DRAM operation.

Synthesizable RTL along with superior analog DLL and propriety implementation flow enables meeting all the critical timing requirements with relative ease. This PHY allows simple SoC integration by using DFI interface alone and requiring fewer programming


Features

  • JEDEC compatible DDR4/3/3L, LPDDR3/2 PHY with max data rate of 3200Mbps (data rate limited by technology node).
  • Hardened single GDS including IO pads
  • Simple controller integration:
  • Fully complaint to DFI 3.1
  • All the DFI pins physically grouped
  • PHY DFI and controller works with same clock
  • PHY independent trainings
  • Industry’s best Power, Performance & area
  • Quick post-silicon DDR bring-up with in-built test and debug features
  • Patented Jitter tolerant and fully automated training algorithms
  • Multi-cycle Write leveling
  • Dynamic Gate training
  • READ and WRITE per-bit-deskewing
  • Proprietary trainings
  • Superior Analog components and IO pads
  • Analog DLL with fine delay steps
  • Duty cycle corrector and sensor
  • Better than foundry IO pads
  • Low power modes and power saving features
  • On-the-fly data width selection with in-rush current control.
  • Auto adaptation to voltage and temperature drifts
  • Self-loopback and DRAM interface BIST, at-speed ATPG and other debug features

Deliverables

  • RF including schematics, database and test bench
  • RTL source code
  • GDS II production licenses
  • Grey Box (Analog/RF GDSII, Digital, FW, SW as source code)
  • White Box (Source Code of complete design data base)
  • SW source code
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