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MIPI MDDI IP

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Description

The MIPI MDDI Unified Solution is compliant with the MIPI Alliance Standard for D-PHY version 1.0 and the VESA Mobile Display Digital Interface Version 1.2 specification.

It consists of 4 lanes, 1 Clock/Strobe lane, 1 bidirectional data lane and 2 unidirectional data lanes, which makes it suitable for display interface applications.

The MDDI and MIPI blocks share the same signal and supply pins. The on-chip receive termination can be used for both MDDI and MIPI. The termination resistors can be calibrated to minimize variations. Once the Display module is qualified it can be used for both MIPI and MDDI resulting in faster time to market and in area and cost savings.


Features

  • Configurable as MIPI Slave or MDDI Client
  • Complies with MIPI Alliance Specification for D-PHY V1.0 and VESA MDDI V1.2
  • Consists of 1 Clock/Strobe lane, 1 bidirectional data lane and 2 unidirectional data lanes
  • Supports both high speed and low-power modes
  • Operates up to 800 Mbps/lane in high speed mode
  • De-Serializers included
  • Optimized for minimal power dissipation & footprint
  • Programmable integrated receive termination
  • Programmable reverse MDDI TX amplitude and CMV(Common Mode Voltage)
  • Built-in testability to enable for full speed production test
  • Silicon Proven in multiple Fabs/Nodes
  • Deliverables

  • RTL code
  • Detailed design document
  • Verification environment
  • Test cases
  • Synthesis environment/script

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