SoC White Box IPs

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Nov 13-16 Munich

Compositor IP

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Description

The compositor sets-up display priorities and mixes real time SD, HD or Quad HD video planes from display processors and memory Flexible IP, configurable as per SoC need Made of one or several MIXER (HW composer) and GDP (versatile Graphics data DMA and processing) Available From 2.25 mm2 (Ultra HD 4K) to 0.46 mm2 (Full HD 2K)

composistor

Features

  • Flexible IP, configurable as per SoC need • Made of one or several MIXER (HW composer) and GDP (versatile Graphics data DMA and processing)
  • Next 4K mandatory features – HDR,2 pixels per clock cycle on GDP+, Capture 10b (same as DVP IP)
  • AXI4 migration
  • Quad HD compositor up to 4 mixers
  • The output color format is RGBsigned – up to 3 video layers & up to 8 GDP layers
  • The output color format is RGBsigned – up to 2 alpha plans & up to 2 capture pipelines
  • Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers
다음 양식을 작성하고받은 편지함에 제품 데이터 시트를 가져 오십시오

T2M의 높은 퀄리티의 사전실증된 아날로그/혼합 시그널, RF, Digital and SW 시스템 해결책은 통신, 소비자와 컴퓨터 제품(IoT, Wearables, 핸드폰, 타블랫, M2M, RCU, set-top boxes, TV, 디비디 플레이어, PC 칩셋등)에 중요한 빌딩 블록으로 사용됩니다. IP는 소비자의 구체적인 요구조건에 따라fab/node 이식이나 전매 특징들을 수정할수 있습니다.