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LIN Bus IP

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Description

The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, designed primarily to be used in automotive applications. Compared to CAN, LIN is slower, but thanks to its simplicity, is much more cost effective. Our Core is ideal for a communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required.

The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as master or slave LIN node, depending on a work mode, determined by the microprocessor/microcontroller. DCD’s controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3. LIN 2.1 and the newest 2.2. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our Core includes programmable timer, which allows to detect timeout and synchronization error. The DLIN is described at RTL level, empowering the target use in FPGA and ASIC technologies

LIN (Local Interconnect Network) is a serial communication protocol, which was created to provide a cost efficient bus communication. The LIN standard is developed by LIN consortium (More). It includes the specification of the transmission medium, the interface between development tools, the transmission protocol and the interfaces for software programming. LIN has been created to decrease costs of automotive networks and replace more expensive CAN in simple application (sensors or actuators). The LIN device can be implemented as a master or as a slave node.
Transmission is initiated by Master Node, which sends the data frame to Slaves Nodes (maximum 15) throat one wire bus.

Features

  • Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification.
  • Automatic LIN Header handling
  • Automatic Re-synchronization
  • Data rate between 1Kbit/s and 20 Kbit/s
  • Master and Slave work mode
  • Time-out detection
  • Extended error detection
  • “Break-in-data” support
  • Available system interface wrappers:
  • AMBA – APB Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
  • Applications

  • Automotive, industrial
  • Embedded communication systems
  • Deliverables

  • Source code
  • Technical support
  • Example application
  • Synthesis scripts
  • Datasheet
  • HDL core specification
  • Installation notes
  • Technical documentation
  • Tests with reference responses
  • ModelSim automatic simulation macros
  • Active-HDL automatic simulation macros
  • VHDL & VERILOG test bench environment
  • Encrypted, or plain text EDIF
  • VERILOG Source Code or/and
  • VHDL Source Code or/and
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