SoC White Box IPs

HDMI V1.3 Rx PHY IP

개요특징Datasheet 요청하기

Description

HDMI receiver PHY (Physical layer) IP is single-port core which is fully compliant with HDMI 1.3a specification. This HDMI Rx PHY supports from 25MHz to 225MHz TMDS clock, and offers a simple implementation for system LSI for consumer electronics like HDTV. The HDMI Rx PHY performs most efficiently with HMDI receiver link IP core.

It is Silicon Proven in many Fab/Nodes including: 130/90/65/55/45/40nm.

Features

  • HDMI version 1.3a compliant receiver
  • Supports DTV from 480i to 1080i/p HD resolution
  • Supports 24bit, 30bit and 36bit color depth per pixel
  • Integrated cable terminator
  • Adaptive equalizer for cable
  • Adjustable analog characteristics
  • PLL band width
  • VCO gain
  • BGR voltage
  • Cable terminator resistance value
  • DLL digital filter characteristics
  • Integrated Audio PLL
  • 3.3V/2.5V/1.0V power supply
  • GLOBAL FOUNDRIES 65nm (C65G) proces
  • Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results

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T2M의 높은 퀄리티의 사전실증된 아날로그/혼합 시그널, RF, Digital and SW 시스템 해결책은 통신, 소비자와 컴퓨터 제품(IoT, Wearables, 핸드폰, 타블랫, M2M, RCU, set-top boxes, TV, 디비디 플레이어, PC 칩셋등)에 중요한 빌딩 블록으로 사용됩니다. IP는 소비자의 구체적인 요구조건에 따라fab/node 이식이나 전매 특징들을 수정할수 있습니다.