USB 3.1 Host Controller IP
DescriptionUSB 3.1 controller are designed for compliance with USB3.1 specification, Revision 1.0 and all associated ECN’s, USB specifications Rev 2.0 and all associated ECN’s. USB 3.1 Host controller is architected to optionally include a High Performance DMA Engine based on xHCI Specification. All buffering associated with the DMA Engine are configurable based on latency and performance requirements. The core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality. USB 3.1 Host Controller based on xHCI specification can be used in systems using any OS which provides xHCI/USB Stacks such as – Android, Linux, Windows. USB 3.1 Host controller exposes either a AXI or AHB Master Interface for the Datapath and an AHB Slave Interface for Register Access. Optionally, a interoperate proven 3rd Party PCIe-AXI/AHB bridge can be provided for use in standard desktop / server applications. Optionally, the controller can be provided with no xHCI Engine and no buffering and operates in a cut-through mode forwarding and receiving USB payloads and managing only the USB protocol. Customer may in this case implement its own differentiated DMA Engine. Optionally, a simple transmit and receive buffer is included in this configuration which can be accessed by software over the slave register access interface which is typically AHB. This option results in very low footprint hardware which can be used in cases where the software can completely manage the USB traffic – including the sequencing of the USB transactions.
- USB 3.1 Host Controller can be configured to support all types of USB transfers – Bulk, Interrupt and Isochronous
- Allows dynamic configuration to support configurable number of endpoints, interfaces, alternate interfaces and configurations.
- USB 3.1 Host Controller can be configured to support any combinations of USB 3.1 interface speeds – SSP (10 Gbps), SS(5 Gbps), HS (480 Mbps), FS(12 Mbps) and LS(1.5 Mbps). Eg combinations are SSP & SS only, SSP & SS & HS only, SSP & SS & HS & FS only, SS Only, SS & HS Only, SS & HS & FS Only, HS & FS Only etc.
- USB 3.1 Host Controller has full support for all low power features of the USB Specification supporting Suspend and Remote Wakeup, USB 3.1 Low Power States – U1/U2/U3 and USB 2.0 Link Power Management states – L1, L2.
- USB Controllers have been Silicon Proven in wide range of products such as Graphics Controller, Flash Storage Controllers, SATA Bridges with support for Bulk Streaming, Embedded Hosts, Docking Stations, Mobile Application Processors, Smart TV, Hubs.
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Extensive clock gating support
- Multiple Power Well Support
- Software control for key features
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- FPGA Platform for Pre-Tape-out Validation