SoC White Box IPs

Visit us at Bluetooth World

Sep 18 -19

Clock Generator (28nm) PLL IP

OverviewFeaturesRequest Datasheet


Clock generator PLL is designed to multiply an input clock signal by an integer 40 and 50. The output is 2.5GHz with 50% duty cycle with quadrature phases.

Available in TSMC90LP, TSMC 65G, TSMC 28HPC, GF 28SLP



  • Input Reference Frequency range – 48MHz – 62.5MHz (90nm), 100MHz (65nm)
  • Output frequency range – 1.9GHz – 2.5GHz (Quadrature O/Ps)
  • Feedback divider value – 40 – 50 (90nm)
  • Output duty cycle – 50% +/- 3%
  • Period Jitter (P-P) – Under NDA
  • Power dissipation (nom) – Under NDA
  • Reset Pulse width (min) – 2us
  • Lock time (Max) – 3us
  • Area – Under NDA
  • Number of PLL supply pkg pins – 2
  • Supply Voltage – 1.2V(Typ) +/- 0.1V (90nm, 65nm), 1V (28nm)
  • Technology Option – TSMC90LP, TSMC 65G, TSMC
Fill the form below, to receive the product datasheet in your inbox

T2M's range of high quality pre-verified, analog/mixed-signal, RF, Digital and SW system solutions, are used as critical building blocks of communications, consumer and computer products including IoT, Wearables, cellular, tablet, M2M, RCU, set-top boxes, TVs, DVD players and PC chipsets. IPs can be modified to meet the customer's specific requirement be it fab/node porting or proprietary features.