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SoC White Box IPs

AES FIPS 197 IP

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Description

The AES core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. Basic core is very small (less than 3,000 gates). Enhanced versions are available that support encryption and decryption for various cipher modes (ECB, CBC, OFB, CFB, CTR), as well as different datapath widths for size/performance tradeoff. The core includes the key expansion logic.

The design is fully synchronous and available in both source and netlist form. Test bench includes vectors from FIPS-197 and the original Rijndael submission. AESAVS tests are also available. AES Core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

Optional data integrity and differential power attack resistance features.

The AES core is available in ECB, CFB, CBC, OFB and CTR modes, and for different datapath widths. Decryption option is also available.

Features

  • Encrypts using the AES Rijndael Block Cipher Algorithm
  • Satisfies Federal Information Processing
  • Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
  • Processes 128-bit data blocks with 8, 16, 32, 64 or 128-bit wide data interface
  • Employs key size of 128,192 and 256 bit.
  • Includes the key expansion function
  • Supports basic modes of AES defined in
  • SP800-38A: ECB, CBC, CFB, OFB and CTR
  • Completely self-contained: does not require external memory
  • Optional countermeasures against power attacks (SPA and DPA)
  • Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected result

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