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SoC White Box IPs

CEC1 66/2112 IP

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Description

The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40 Gbps/100 Gbps operation). The encoder and decoder functions are completely independent and packaged as two sub-cores, CEC1-66/2112E and CEC1-66/2112D respectively. Decoder corrects a single burst error of upto 11 bits.

Features

  • Small size
  • Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
  • 10G/40G/100G Ethernet MAC-friendly interface
  • Practically self-contained: requires only memory for one 2112-bit block in the decoder.
  • Flow-through design; low latency
  • Benefits

  • The CEC1-66/2112E core implements the FEC encoder per section 74 of the IEEE 802.3 standard.
  • The CEC1-66/2112D core implements the FEC decoder per section 74 of the IEEE 802.3 standard.
  • Applications

  • IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40 Gbps/100 Gbps operation)
  • Deliverables

    HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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