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SoC White Box IPs

26C92 IP

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Description

The D26C92 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681 with added features and deeper FIFOs.

It contains: 8 character receiver, 8 character transmit FIFOs, WATCH dog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts.

The D26C92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system, furthermore provides modem and DMA interface. The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate GENERATOR and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the UART particularlyattractive for dual-speed channel applications such as clustered terminal systems.

Features

  • Software compatible with SC26C92, SCC2692 and SCN2681 UARTs
  • Configuration capability
  • Dual full-duplex independent asynchronous receiver/transmitters
  • 8 character FIFOs for each receiver and transmitter
  • Programmable data format:
  • 5 to 8 data bits plus parity
  • ODD even, no parity or force parity
  • 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
  • 16-bit programmable Counter/Timer
  • Programmable baud rate for each receiver and transmitter selectable from:
  • 27 fixed rates: 50 to 230.4k baud
  • Other baud rates to 230.4k baud at 16X
  • Programmable user-defined rates derived from a programmable counter/timer
  • External 1X or 16X clock
  • Parity, framing, and overrun error detection
  • False start bit detection
  • Line break detection and GENERATION
  • Programmable channel mode:
  • Normal (full-duplex)
  • Automatic echo
  • Local loopback
  • Remote loopback
  • Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
  • Multi-function 7-bit input port:
  • Can serve as clock, modem, or control inputs
  • Change of state detection on four inputs
  • Multi-function 8-bit output port:
  • Individual bit set/reset capability
  • Outputs can be programmed to be status/interrupt signals
  • FIFO states for DMA and modem interface
  • Versatile interrupt system:
  • Single interrupt output with eight maskable interrupting conditions
  • Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
  • Each FIFO can be programmed for four different interrupt levels
  • WATCHdog timer for each receiver
  • Maximum data transfer rates: 1X – 1Mb/sec, 16X – 1Mb/sec
  • Automatic wake-up mode for multidrop applications
  • Start-end break interrupt/status
  • Detects break which originates in the middle of a character
  • Power down mode
  • Receiver timeout mode
  • Benefits

  • D-26C92
  • Applications

  • Serial Data communications applications
  • Modem interface
  • Embedded microprocessor boards
  • Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • PHONE& email support

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