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SoC White Box IPs

8259-Interupt Controller IP

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Description

The D8259 is a soft Core of Programmable Interrupt Controller. It is fully compatible with the 82C59A device. Our efficient IP core can manage up to 8-vectored priority interrupts for the processor. Moreover, you can also program it to cascade and gain up to 64 vectored interrupts. And if it's not enough, you can always get more than 64 vectored interrupts. Just program our IP Core to the Poll Command Mode. The D8259 can operate in all 82C59A modes and it supports all 82C59A features. The D8259 Package includes fully automated testbench. Thanks to complete set of tests, you can easily validate the whole package at each stage of SoC design flow.

Features

  • 8 vectored priority interrupts
  • Up to sixty-four vectored priority interrupts with cascading
  • Support for all 82C59A modes features
  • MCS-80/85 and 8088/8086 processor modes
  • Fully nested mode and special fully nested mode
  • Special mask mode
  • Buffered mode
  • Pool command mode
  • Cascade mode with master or slave selection
  • Automatic end-of-interrupt mode
  • Specific and non-specific end-of-interrupt commands
  • Automatic and Specific Rotation
  • Edge and level triggered interrupt input modes
  • Reading of interrupt request register (IIR) and in-service register (ISR) through data bus
  • Fully synthesizable HDL Source Code
  • Static design and no internal tri-states
  • Applications

  • Embedded microprocessor boards
  • Deliverables

  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support

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