SoC White Box IPs

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D32Pro IP

OverviewFeaturesRequest Datasheet

Description

The D32PRO is royalty-free silicon proven, high performance soft core of a single-chip 32-bit em-bedded controller, with Floating Point Coproces-sor. Thanks to its increased code density, the D32PRO meets the power and size requirements of new connected devices. That’s why both power and performance of this IP Core predestine it as a real alternative for ARM Cortex M0/M0+/M1/M3 in the deeply embedded market and especially for emerging market of connected devices (IoT). Re-sponding to continuing demands for less power drain in system-on-chip (SoC) designs, DCD has developed an instruction set aimed at reducing the size of system’s instruction memory.
The D32PRO is aimed at low-power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Low Energy. Nevertheless the core is perfect for embedded systems that require greater computational per-formance and system complexity by supporting dual- and multi-core systems as well as improved code density. DCD’s IP Core is fully customizable – it is delivered in the exact configuration to meet customer’s requirements.
The D32PRO is offered with great variety of peripherals like USB, SPI, LCD, HDLC, UART, Ethernet MAC, CAN, LIN, RTC and many more – ready to be implemented with the CPU. The D32PRO is delivered with fully automat-ed test bench and complete set of tests, allowing easy package validation at each stage of SoC design.

d32pro


Features

  • ASIC Silicon proven architecture
  • Performance up to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz
  • Small footprint starting at 10.6k / 6.7k ASIC gates
  • Dynamic power below 7 uW/MHz in 90nm
  • Very high clock frequency up to 1 GHz in modern ASIC technologies
  • Configurable 32-bit Harvard architecture
  • Fifteen 32-bit general Purpose registers
  • Up to 256 MB of Code Space with encrypted bootloader
  • Up to 256 MB of Data Space
  • Built-in configurable Floating Point co-processor using dedicated instructions
  • Configurable 32-bit hardware multiplier
  • Configurable 32-bit hardware divider
  • Configurable 32-bit hardware shifter
  • Low power consumption by Advanced Power Management Unit
  • Advanced Power management mode
  • Switchback feature
  • Stop mode
  • Deliverables

  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support

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