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SoC White Box IPs

GSM GPRS EDGE SoC White Box IP

OverviewFeaturesRequest Datasheet

Description

The T2M7271 is the industry's first IP solution to support the IEEE 802.11ah AP standards. To implement the fully integrated modem, the IP includes a baseband physical layer, Lower MAC layer, and Upper MAC layer.

T2M7271 is designed to be associated up to 8,191 devices. Target Wake Time (TWT) and Restricted Access Window (RAW) functions are implemented for low power operations.Security features such as AES-CCMP and IEEE 802.11w are also included. The IP’s physical layer supports up to 15Mbit/s. It supports the traveling pilot function for the outdoor IoT environments affected by high Doppler effect.

T2M7271 is designed to be independent of the silicon process. As the MAC layer is designed to respond quickly to changes in the specification and feature, this IP can be utilized as the wireless connectivity solution for variable use cases including sensors and meters, backhaul sensors and meter data, and extended range uses of Wi-Fi.

T2M7271

Features

  • Complies with IEEE 802.11ah draft 5.0
  • Prepared for upcoming WFA ERah certification
  • Low-Power and High-Throughput 1x1 IEEE 802.11ah-AP 
  • Modulation modes: - OFDM with BPSK, QPSK, 16QAM, 64QAM 
  • Supported data rates: - 1MHz BW: 150Kbps to 3.3Mbps - 2MHz BW: 650Kbps to 6.5Mbps - 4MHz BW: 1350Kbps to 15Mbps

Benefits

  • Available as SoC White Box IP

Applications

  • The wireless connectivity solution for variable use cases including sensors and meters, backhaul sensors and meter data, and extended range uses of Wi-Fi.

Deliverables

  • Datasheets
  • Hard macro containing IEEE 802.11ah AP baseband (PHY, MAC H/W)
  • MAC S/W code
  • Test vectors and simulation model
  • Integration support

Tech Specs

PHY layer: - Data rate up to 15 Mbps - Supports for 1/2/4MHz bandwidths - MCS 0 to 7 and 10 - Support Short GI - Support Traveling Pilot

MAC layer: - Flexible architecture - Supports up to 8,000 stations - Supports relay mode (for extended range) - Support station scheduling: Target Wake Time (TWT) , Restricted Access Window (RAW).

Security: AES-CCMP • IEEE 802.11w

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OverviewFeaturesRequest Datasheet

Description

The RF transceiver IP is a complete radio front-end optimized for sub-GHz band, IEEE 802.11ah SoC implementation, based on the industry’s proven direct conversion transceiver architecture. This transceiver IP has fully integrated power amplifiers along with the capability to support various commercial external FEM. RF IO ports are single-ended and a fractional-N synthesizer while the power amplifiers and LDOs are fully integrated for minimum BOM and PIN counts.

A special LPO for the high Sleep Clock Accuracy (SCA) is also integrated for the low power applications. This Radio IP supports various radio calibration functions such as TRX IQ mismatch calibration, LO feedthrough calibration, DC offset cancellation, fast AGC, VCO calibration, VCO temp

variation compensation, bias calibration, LPF corner frequency compensation, battery monitoring, and temperature monitoring.

The internal, digitally-controlled gain stages at the RF and BB levels provide both low noisefigure and large dynamic range of the receiver. Furthermore, the transmitter has more than30dB gain range, which provides a wide output power range. Cutoff frequency of the baseband filters are calibrated with an internal RC compensation scheme while the low pass filter supports modulation bandwidths up to 16MHz. A crystal oscillator, which is connected to a low cost external crystal, is also integrated. The SPI interface controls most of the transceiver functions.

7141

Features

  • Low power sub-GHz band transceiver for IEEE 802.11ah
  • Compliant with IEEE 802.11ah draft 5.0
  • Support up to 16MHz channel BW
  • Integrated power amplifiers
  • Integrated LDOs
  • TX LOFT/IQ mismatch calibration
  • RX IQ mismatch calibration
  • Fast AGC using built-in RSSI
  • LPF calibration
  • PLL calibration
  • Bias current calibration
  • Support of external FEM modules
  • Internal temperature sensing
  • Internal battery monitoring
  • Benefits

  • Available as SoC White Box IP
  • Deliverables

  • Datasheets
  • Hard macro containing IEEE 802.11ah radio
  • Integration support with baseband
  • Process node: TSMC 40 LP
  • Tech Specs

  • Single-ended RF ports
  • Two supplies : 1.4V, 2.0 ~ 3.6V
  • Supply current: RX: 10mA @ 1.4V TX: 10mA @ 1.4V 13mA @ 2.0V(Pout = 0dBm)
  • Frequency band: 750 ~ 950 MHz
  • Modulation: BPSK, QPSK, 16QAM, 64QAM
  • Linear TX output power: 0dBm
  • TX gain range: 30dB
  • RX noise figure : < 3dB
  • RX gain range: 80dB
  • Max. input power: -10dBm
  • Phase error: < 0.6 deg for 64QAM
  • EVM: < -31dB @ 64QAM
  • LPO accuracy: 500ppm

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OverviewFeaturesRequest Datasheet

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OverviewFeaturesRequest Datasheet

Description

The T2M6271 is silicon-proven dual band IEEE 802.11a/b/g/n/ac Baseband/MAC wireless solution for low-power and high-throughput mobile and Internet of Things (IoT) applications. It supports both mandatory and optional features of the IEEE 802.11a/b/g/n/ac standards as well as the corresponding Wi-Fi Alliance certifications. The single stream 1x1 IEEE 802.11n mode provides up to 433Mbps data rate.

The Baseband IP supports all mandatory IEEE 802.11a/b/g/n/ac features, including several optional features such as 256 QAM, LDPC, SGI, STBC, and SU/MU Beamforming. It also supports all the rates specified in IEEE 802.11a/b/g/n/ac. Meanwhile, the MAC IP supports all mandatory features as well as several options such as AMSDU, A-MPDU, Quiet Channel, and Link Adaptation. In addition, it is WFA certified for several key certifications like IEEE 802.11ac, PMF, WPA/WPA2, Wi-Fi Direct, Wi-Fi Aware, WiFi Passpoint R2, TDLS, WMM-PS, and WMM-AC.

The T2M6271 has been designed to achieve the lowest power consumption with a combination of several proprietary techniques for low-power mobile wearable electronics and IoT applications.

802-11-ac

Features

  • Compliant with IEEE 802.11a/b/g/n/ac
  • Low-Power and High-Throughput 1x1 Dual Band IEEE 802.11ac
  • Data rate up to 433 Mbps
  • 256-QAM, 80MHz bandwidth for high data rate
  • LDPC and SGI support
  • Supports SU/MU Beamforming packet reception and feedback
  • Optional A-MSDU, A-MPDU, Quiet Channel, and Link Adaptation support
  • Benefits

  • Available as SoC White Box IP
  • Applications

  • Low-power mobile wearable electronics
  • IOT
  • Deliverables

  • Datasheets
  • Hard macro containing dual band IEEE 802.11ac radios
  • Integration support with baseband
  • Process node: TSMC 40 LP
  • Tech Specs

  • 22/20/40/80MHz bandwidths
  • 1, 2, 5.5, 11, 6.5 to 433 Mbps
  • BPSK, QPSK ,16QAM, 64QAM, 256QAM, DBPSK, DQPSK, CCK
  • LDPC and SGI support
  • Supports SU/MU Beamforming packet reception and feedback
  • Encryption: AES, TKIP, WEP, WAPI
  • Wi-Fi Alliance Certified: IEEE 802.11ac, PMF, WPA/WPA2, Wi-Fi Direct, Wi-Fi Aware, Wi-Fi Passpoint R2, TDLS, WMMPS and WMM-AC support

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OverviewFeaturesRequest Datasheet

Description

This dual band RF transceiver IP is a complete radio front-end, optimized for IEEE 802.11a/b/g/n/ac SoC implementation, based on the industry’s proven direct conversion transceiver architecture. The RF transceiver IP has fully integrated power amplifiers along with the capability of various commercial external FEM support. RF IO ports are single-ended and a fractional-N synthesizer while the power amplifiers and LDOs are fully integrated for minimum BOM and PIN counts.

The IP supports various radio calibration functions such as PAPD, TRX IQ mismatch calibration, LO feedthrough calibration, DC offset cancellation, fast AGC, VCO calibration, VCO temperature variation compensation, bias calibration, LPF corner frequency compensation, battery monitoring, and temperature monitoring.

The internal, digitally controlled gain stages at the RF and BB levels provide both low noise figure and large dynamic range for the receiver. In addition, the transmitter has more than 30dB gain range, which provides a wide output power range. The cutoff frequency of the baseband filters are calibrated with an internal RC compensation scheme while the low pass filter supports modulation bandwidths up to 80MHz. A crystal oscillator, which is connected to a low cost external crystal, is also integrated. The SPI interface controls most of the transceiver functions.

6231-ac-rf

Features

  • Dual band transceiver for IEEE 802.11ac
  • Compliant with IEEE 802.11a/b/g/n
  • Supports up to 80MHz channel BW
  • Integrated power amplifiers
  • Integrated LDOs
  • TX LOFT/IQ mismatch calibration
  • RX IQ mismatch calibration
  • Fast AGC using built-in RSSI
  • PAPD calibration
  • LPF calibration
  • PLL calibration
  • Bias current calibration
  • Support of external FEM modules
  • Internal temperature sensing
  • Internal battery monitoring
  • Benefits

  • Available as SoC White Box IP
  • Deliverables

  • Datasheets
  • Hard macro containing dual band IEEE 802.11ac radios
  • Integration support with baseband
  • Process node: TSMC 40 LP
  • Tech Specs

  • Single-ended RF ports Two supplies: 1.4V, 2.7V to 4.8V
  • Supply current: - RX: 75mA @ 1.4V, 10mA @ 3.3V
  • - TX: 60mA @ 1.4V 80mA @ 3.3V(Pout = +3dBm) 180mA @ 3.3V(Pout = +18dBm)
  • Frequency band: - 2.4 to 2.5GHz, 4.9 to 5.8GHz
  • Modulation bandwidth: - 10M, 20M, 40M, 80M Linear TX output power: +18dBm TX gain range: 30dB RX noise figure: < 3.5dB RX gain range: 80dB RX IIP3: -13dBm RX IIP2: +20dBm
  • Phase error: < 0.4 deg. for IEEE 802.11ac
  • Fast TX/RX switching: < 5us EVM: < -35dB @ 256QAM

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OverviewFeaturesRequest Datasheet

Description

A unique opportunity to licence the "white box source code" design data base of a Tier 1 semiconductor's high volume mass production WiFi Dual RF Band "SoC" that has been shipped in Tier 1 OEM products.

This IP is delivered as the complete chip design data base enabling internalization, customization and porting of the design to future process nodes.

The IP comes with all certification certificates and SW and the design data base can be TO and in volume production with in 6 months of purchase.

The commercial terms are single NRE payment, no royalties, unlimited usage, making it a very cost effective, low risk, WiFi technology access.

147652006122l_stb-rf

Features

  • Dual Band 2.4/5 Ghz RF with integrated PA
  • Certified in Tier 1 handset shipped in high volume
  • Best-in-class IOT with comprehensive coverage
  • Ultra low power consumption with innovative host offloading features
  • RF design includes best in class cellular blocker and innovative LTE & BT Co-Existence
  • Integrated SMPS with direct battery connection
  • Flexible firmware host partitioning architecture catering to different customer system partitioning
  • Reduced PCB footprint with minimal external components
  • Benefits

  • A mass production chip that is available as a white box IP license with modification rights and unlimited usage
  • Applications

  • IoT
  • M2M
  • Cellular
  • Automotive
  • Deliverables

  • Design Data Base of chip
  • Schematics
  • Layout
  • Source Code
  • Certification Certificates
  • Chip Test program

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OverviewFeaturesRequest Datasheet

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OverviewFeaturesRequest Datasheet

Description

A unique opportunity to licence the "white box source code" design data base of a Tier 1 semiconductor's high volume mass production WiFi Dual RF Band "SoC" that has been shipped in Tier 1 OEM products.

This IP is delivered as the complete chip design data base enabling internalization, customization and porting of the design to future process nodes.

The IP comes with all certification certificates and SW and the design data base can be TO and in volume production with in 6 months of purchase.

The commercial terms are single NRE payment, no royalties, unlimited usage, making it a very cost effective, low risk, WiFi technology access.

soc-white-box-ip

Features

  • Dual Band 2.4/5 Ghz RF with integrated PA
  • Certified in Tier 1 handset shipped in high volume
  • Best-in-class IOT with comprehensive coverage
  • Ultra low power consumption with innovative host offloading features
  • RF design includes best in class cellular blocker and innovative LTE & BT Co-Existence
  • Integrated SMPS with direct battery connection
  • Flexible firmware host partitioning architecture catering to different customer system partitioning
  • Reduced PCB footprint with minimal external components
  • Benefits

  • A mass production chip that is available as a white box IP license with modification rights and unlimited usage
  • Applications

  • IoT
  • M2M
  • Cellular
  • Automotive
  • Deliverables

  • Design Data Base of chip
  • Schematics
  • Layout
  • Source Code
  • Certification Certificates
  • Chip Test program

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OverviewFeaturesRequest Datasheet

Description

EtherMind Software IP includes versions v4.0, v4.1 and v4.2 of Bluetooth Smart & Bluetooth Smart Ready Stack & Profiles. EtherMind is a comprehensive offering which consists of all the mandatory and optional features of the core stack and all the adopted profiles.

This IP has been integrated into multiple products and is designed to suit the needs of product OEMs, ODMs and Semiconductor companies.

EtherMind enables customer to reduce market risk of integrating Bluetooth in the product while accelerating the development cycle. The large base of customers is testimony of the IP’s high quality, proven reliability, functionality and portability as per the adopted Bluetooth specifications.

Mindtree-dual-mode

Features

  • Bluetooth SIG Qualified, Production Proven IP
  • Proven Interoperability
  • Low MIPS and Memory Footprint for Stack & Profiles
  • Platform and Operating Systems (OS) agnostic and is designed for Easy Portability
  • Proven on all popular 32 bit and 16 bit MCUs and a variety of OS
  • Non-Blocking Architecture
  • Compile time options for Feature Configuration
  • Benefits

  • Tested for interoperability with more than 200 smart phone models
  • Proven in all UnPlugFests
  • Modules are compile-time configurable
  • Same architecture and codebase across can be ported across Multiple devices
  • Demonstrates the flexibility of the architecture
  • Easy for testing Interoperability across range of devices
  • Applications

  • PNDs, Resource Constrained Headsets, Watches and Healthcare, IOT devices
  • Deliverables

  • Source Code of Transport Abstraction Layer and Operating System Abstraction Layer
  • Source Code of sample applications to illustrate the use of APIs
  • API Documents for Smart Mesh Profile and Encryption blocks
  • API Documents for the Transport Abstraction Layer
  • API Documents for the Operating System Abstraction Layer
  • User manual describing how to build and run the sample application

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OverviewFeaturesRequest Datasheet

Description

Proven IPv6 suite which resides over the Bluetooth Smart or 802.15.4 layers. IPv6 suite has been built grounds up to meet the needs of embedded systems. The IPv6 suite is optimized for Memory and MIPS and implemented in ANSI C to enable portability across processor platforms. The IPv6 Suite also provides clean abstraction layers to enable it to work across Operating Systems and various lower layer implementations of BLE Host stack. Specifically for Bluetooth Smart - The IPv6 Suite supports 6LoBTLE, IPv6, CoAP, UDP and Internet Protocol Support Profile (IPSP). This enables any individual Bluetooth capable device to be wirelessly connected and addressable over the Internet. This capability, together with the low power consumption offered by BLE is ideal for the wireless Internet of Things network. IPv6

Features

  • Low Memory Footprint - Less than 15 KB Flash and very low RAM requirement
  • Platform and Operating Systems (OS) agnostic and is designed for Easy Portability
  • 6LoBTLE implementation
  • Bluetooth SIG Qualified implementation of Internet Protocol Support Profile (IPSP
  • Applications

  • Internet of Things ( IOT)
  • Deliverables

  • Technical Documentation
  • Source Code with the test environment
  • Integration support

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OverviewFeaturesRequest Datasheet

Bluetooth Low Energy v5 and IEEE 802.15.4 (ZigBee 3) compliant RF Transceiver + Modem IP silicon proven in 55 & 40nm ULP FLASH process nodes. The radio supports 2Mbps, Long Range and is compliant with Bluetooth® Low Energy Core Configuration (Bluetooth Smart) Version 5. The RX and TX currents are optimized to be ~5mA from 0.9V supply. The IP includes the modem and integrates all the calibrations required for the radio operation in a SOC. The radio analog hard IP including the RF pad-ring occupies less than 0.5sqmm area. The radio provides best in class RX and TX metrics at highly optimized area and current. Optional integrated RF matching network enabling direct connection to the antennae with minimal loss in performance.

1470035787ble5-0

FEATURES

    • BLE 5 & IEEE 802.15.4 (ZigBee) Compliant : 2Mbps data rate, Long Range support
    • Area ~ 0.5mm2
    • Maximum Tx. Power: +7dBm
    • Maximum Junction Temperature: +125ºC
    • Ultra-Low Power Operation (RFIP + modem):  RX (@1Mbps): 5.5mA@0.9V, TX (@ 0dBm): 5.6mA@0.9V
    • Excellent RX Sensitivity:  -96 dBm (Uncoded PHY, 1Mbps), -93 dBm (2Mbps)
    • Integrated matching network (optional)
    • Integrated LDOs
    • Flexible SOC Interface, pre-integrated with:  ARM, CEVA, Mindtree
    • Integrated with ESD protected I/O pads
    • CSP & QFN Package support
    • Technology Nodes silicon proven:
    • TSMC55 ULP FLASH
    • SMIC55 LP FLASH
    • TSMC40 ULP
    • GF40 (3Q17)

Deliverables

  • GDSII or source code
  • Digital Source Code RTL
  • Complete design transfer

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OverviewFeaturesRequest Datasheet

Description

BlueLitE is a Bluetooth core certified by BT SIG to meet the specifications version 5 (Bluetooth low energy) for single mode.

The BlueLitE product line has two component IPs. The BlueLitE-SP (Stack and Profiles) and the BlueLitE-LP (Link layer and Physical layer)

BlueLitE Link Layer

The BlueLitE product line has two component IPs. The BlueLitE-SP (Stack and Profiles) and the BlueLitE-LP (Link layer and Physical layer)

The link layer is a hardware-firmware implementation. While the time critical protocol procedures are handled in the hardware, the firmware implements the link layer control protocol (LLCP), Security and host command and event handling.

The physical layer is a digital hardware implementation and performs the GFSK modulation & demodulation and provides features for receive AGC and RSSI measurements.

Pre-integrated with major RF IPs from CSEM, AURA, Catina, etc.

BlueLitE SW Stack & Profiles

BlueLitE-SP is the stack and profile solution for single mode Bluetooth low energy Specification. This consists of LE-HCI, LE-L2CAP, LE-SM, LE-GAP, GATT, ATT and a suite of all profiles adopted by SIG. The BlueLitE-SP is designed to be portable on variety of platforms including 8 bit microcontrollers with minimal system resources.

9-main-bluetooth-low-energy-4-1-bluetooth-smart-baseband-controller-ip

Features

  • Implements Link layer and physical layer of LE controller specification
  • Supports all mandatory and optional features
  • Supports all device roles and states
  • Architected for very low power and low memory footprint
  • Integrated Power Management
  • Firmware portable for 8/16/32-bit microcontrollers
  • Deliverables

  • Source Code of Transport Abstraction Layer and Operating System Abstraction Layer
  • Firmware source code
  • Technical Documnetation
  • OS and MCU abstraction layers for portability to any SoC platform
  • Support for multiple processor bus and flexible RF Interface
  • BLE 5 BQB qualified

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OverviewFeaturesRequest Datasheet

Description

The icyTRX ultra-low- power RF transceiver is designed to meet standards such as Bluetooth Low Energy (Bluetooth Smart), 802.15.4 PHY Layer (e.g. ZigBee), and proprietary standards with data-rates from 62.5 kBit/s up to 4 Mbit/s. icyTRX offers less than 5.5mW consumption in receive mode from a 1.0V supply. icyTRX is a complete transceiver that is designed for miniaturization, yielding a die size of less than 1.6 mm2 in 55 nm CMOS, requiring minimal external components thanks to high degree of integration. icyTRX is designed for easy integration into ASICs and SoCs. Available under license as an embedded IP block for integration in CMOS SoCs and ASICs. This is a mature, production proven RF IP. 

Samples and development kits are available

1470035787ble5-0

Features

    • Exceeds BLE v5 and ZigBee v3 requirements: 2MBPS, Long Range
    • Power Consumption:
    • 1V to 1.3V (functional down to 0.9V)
    • RX current: 5.3 mA (@1 MBit/s)
    • TX current: 8.6 mA (@ 1 dBm)
    • Bluetooth 5 sensitivity:
    • -94 dBm at 2 Mbit/s
    • -97 dBm at 1 Mbit/s (4x)
    • -105 dBm at 125 kbit/s (Long Range S=8)
    • -101 dBm at 500 kbit/s (Long Range S=2)
    • No calibration needed, ultra fast settling
    • Single Rx and Tx port
    • Fully integrated FSK-based modem, with
    • programmable pulse shape, data rate and modulation index
    • Partial Link layer functionalities, including :automatic packet handling, CRC, AES-CCM, separate Rx and Tx FIFOs
    • Proprietary modes with adjustable bitrate from 62.5 kBit/s up to 4 Mbit/s
    • Pre-integrated with ARM, CEVA, Mindtree
    • Silicon area <1.6 mm (55 nm CMOS)

Applications

    • Wearable sensors
    • Wireless sensor networks
    • Smart watches+fitness bands

Availability

    • GDSII: TSMC55 ULP FLASH, GF55 ULP
    • Samples and EVKs available

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OverviewFeaturesRequest Datasheet

Description

Smart Mesh IP Suite offers the Smart Mesh Profile and Application Level Encryption. The Smart BLE Mesh Profile is compatible with BT-SIG's draft Smart Mesh Profile specification..

Smart Mesh over Bluetooth Smart is built grounds up to meet the needs of embedded systems. It is optimized for Memory and MIPS. The IP suite is implemented on ANSI C to enable portability across processor platforms.

Features

  • Flooding Mesh Network: Uses broadcast channels to transmit messages so that other nodes can receive messages and relay these messages by re-transmitting them, thus extending the range of the original message
  • Bearer Layer:Advertising (ADV) Bearer (Advertising data type to encapsulate the mesh packet) & GATT Bearer (Attribute protocol used to encapsulate the mesh packet) –Support by Q2-2014
  • Provisioning Bearer (PB): Provisioning of nodes on the BLE-Mesh through PB-ADV, PB-Mesh and PB-GATT
  • Platform and Operating Systems (OS) Agnostic and is designed for Easy Portability : No limitation on number of Mesh Nodes
  • Advanced Encryption Standard (AES) blocks supports are CMAC (IETF RFC 4493) and CCM (IETF RFC 3610), as per draft BT-SIG specification requirements
  • Deliverables

  • Smart Mesh IP implemented in ANSI C consisting of:
  • Smart Mesh Profile (Servers, Clients roles)
  • Application based encryption using 128-bit AES CCM (IETF RFC 3610) and CMAC (IETFRFC 4493)
  • Source Code of Transport Abstraction Layer and Operating System Abstraction Layer
  • Source Code of sample applications to illustrate the use of APIs
  • Documentation

  • API Documents for Smart Mesh Profile and Encryption blocks
  • API Documents for the Transport Abstraction Layer
  • API Documents for the Operating System Abstraction Layer
  • User manual describing how to build and run the sample application

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OverviewFeaturesRequest Datasheet

Description

The modulation and spreading functions for the O-QPSK PHYs are processed through 3 steps. First, each 4 bits are gathered to represent 1 symbol which has a value from 0 to 15. Second, each symbol is used to select among 16 PN sequences called chip. Finally, each chip is modulated using O-QPSK with half-sine pulse shaping. Once a preamble is detected, the Start of Frame Delimiter (SFD), frame length, and other receiver status information is sent to the upper layer. Additionally, the payload data is written to the received data buffer to create the PSDU packet, which is transferred to the MAC layer when requested. The PHY notifies the MAC layer for arrival of MAC Protocol Data Unit (MPDU) along with the LQI information via an interrupt. If a valid preamble is not detected, it gives feedback to the packet time error detection block to restart the energy detection process. The design includes ED and LQI circuits to support CCA modes by MAC defined in IEEE 802.15.4. The design includes a standard 32-bit AHB-lite, slave interface version 3.0, with registers as defined in the Register Description section of the Datasheet.

Features

  • Low power transceiver PHY IP for ZigBee applications, compliant with IEEE 802.15.4 standard.
  • Efficient demodulator with frame synchronization and frequency offset compensation.
  • Supports 2 MHz IF input (reconfigurable on request).
  • Offset-QPSK (OQPSK)
  • Chip rate: 2000 kchips/sec
  • Bit rate: 250 kbits/sec
  • Symbol rate: 62.5 ksymbols/sec
  • Spreading sequence: 16-ary orthogonal
  • Support a carrier frequency offset (CFO) up to 250 KHz
  • Sampling frequency: 8 MHz (reconfigurable on request)
  • Uses single-bit limiter (8-bit ADC version available on request)
  • AHB-Lite bus interface (other interfaces available on request)
  • Applications

  • Home automation
  • Health care
  • Smart energy
  • Smart metering Utility Network (SUN)
  • Deliverables

  • Synthesizable Verilog
  • System Model (Matlab) and documentation
  • Verilog Test Benches
  • Documentation

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OverviewFeaturesRequest Datasheet

Description

This IP is a fully integrated system-on-chip radio transceiver targeting Smart Grid applications. The performance is tailored for extremely low power operation to be used in sensor monitoring networks and remote control for wireless networks. Transmitter output power ranges from -8 to +15 dBm, while receiver sensitivity is -110 dBm at 25kbps data rate.

Additional peripherals such as ADC, SPI, I2C, UART, I2S and timers are all included on the same chip, resulting in a compact system solution.This is ideal for portable applications in frequency ranges 863-928 MHz , in particular those needing long battery life and/or signal processing, such as AMR, WSN and medical.

Features

  • Ultra-low power 863-928 MHz transceiver
  • Low voltage operation from 3.6 V down to 1.0? V
  • Minimum current standby mode with RTC based on 32 ?kiHz crystal oscillator: 1? µA at 37?°C
  • Low continuous Rx current: 3.5 mA (1 ?V)
  • RF data rate up to 400 kb/s
  • Rx sensitivity -110 dBm at 25 kb/s in FSK modulation, -115 dBm at 2 kb/s in OOK modulation
  • Digital RSSI: 3 dB/step from noise level up to -30 dBm
  • Flexible modulation: FSK, OOK, 2-FSK, 4-FSK, QPSK
  • 16/32-bit DSP/CPU, 120 µA/MHz, dual MAC
  • Software development kit: gcc, gdb, ISS, Eclipse
  • 96 kiB low leakage SRAM (program and data)
  • Integrated ADC (10 kS/s), power management, LED current sources
  • Standard digital interfaces: SPI, UART, I2C, I2S and GPIO
  • ETSI EN300-220 V2.2.2 and FCC part 15.247 and 15.249 compliant
  • Applications

  • Automatic Meter Reading (AMR)
  • Wireless Sensor Networks (WSN)
  • Medical and Body Area Networks (BAN)
  • Home automation
  • Deliverables

  • Samples and evaluation kits are available
  • Packaging options: bare die or QFN
  • Derivatives custom requirements

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OverviewFeaturesRequest Datasheet

Description

ZBOSS is a product line of IP for ZigBee core specifications version r20. The ZBOSS product line has two component IPs, the Stack + Profiles and the MAC, Link layer and Physical layer. The product is designed to work with the "Bluetooth Smart / ZigBee RF Transceiver IP-IoT" providing a complete SoC implementation.

Stack + Profiles

  • ZBOSS stack and profile solution for ZigBee Pro core stack based on r20 (2012) specification.
  • Core stack includes:
  • - Mac layer
  • - OS-dependent layer
  • - Core stack:
  • Network layer
  • APS layer (application support)
  • ZDO layer (ZigBee Device Object)
  • Security layer
  • ZDP (ZigBee Device Profile)
  • - ZCL (ZigBee Cluster Library)
  • The ZBOSS SW is designed to be portable on variety of platforms including 8 bit micro controllers with minimal system resources.

MAC, Link layer and Physical layer

The "MAC, link layer and physical layer (Modem)" implementation for 802.15.4 specifications.

The link layer is a hardware-firmware implementation. While the time critical protocol procedures are handled in the hardware, the firmware implements the link layer control protocol (LLCP), Security and host command and event handling.

The physical layer is a digital hardware implementation and performs the modulation & demodulation and provides features for receive AGC and RSSI measurements.

The SW is in production shipping with many 802.15.4 chipsets supporting ZigBee Pro, RF4CE, 6Lowpan, and soon Thread support.

Features

  • Supports complete 802.15.4 Modem, Link Layer and MAC
  • Supports ZigBee Pro, RF4CE, 6Lowpan, Thread
  • Supports all mandatory & optional features
  • Supports all adopted profiles and services
  • Architected for low memory footprint
  • Portable across 8/16/32-bit microcontrollers
  • Application development framework for all implemented profiles
  • ZHA, ZLL, ZGP, ZSE and ZBA
  • Home Automation, Light Link,Green Power etc. Profiles supported
  • Certified ZigBee Pro core stack
  • Deliverables

  • C Source Code for all software
  • RTL for HW
  • Simulation test bench with regression test suit
  • Reference Platform Drivers

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OverviewFeaturesRequest Datasheet

Description

A low-power, highly-integrated SoC solution, the Zigbee chip is a true 2.4GHz SoC solution with Zigbee compliant platform and supports IEEE 802.15.4 Standard. Combined with the Zigbee stack, the solution can be used for a wide range of applications and is perfect for creating interoperable solution for home or office usage.

The chip is designed to offer high integration, ultra-low power application capabilities. It integrates strong 32-bit MCU, 2.4G Radio, 16KB SRAM, 128/256/512KB external FLASH or 512KB internal Flash, 14bit ADC with PGA, 6-channel PWM, three quadrature decoders, a hardware keyboard scanner (Keyscan), abundant GPIO interfaces, multi-stage power management module and nearly all the peripherals needed to construct a powerful wireless Zigbee/IEEE 802.15.4 system.

With the high integration level, few external components are needed to satisfy customers’ ultra-low cost requirements.

Features

  • Embed 32-bit high performance MCU with clock up to 48MHz
  • external 128/256/512KB FLASH or internal 512KB Flash
  • Data memory: 16KB on-chip SRAM
  • 12MHz/16MHz Crystal and 32KHz/32MHz embedded RC oscillator
  • A rich set of I/Os:

  • Up to 35/37/21 GPIOs depending on package option
  • SPI, I2C, UART, USB, Debug Interface
  • Up to 6 channels of PWM
  • Sensor

  • 14bit ADC with PGA;
  • Temperature sensor
  • Three quadrature decoders
  • Embeds hardware AES
  • Compatible with USB2.0 Full speed mode
  • Operating temperature: -40~+85 industrial temperature range
  • 2.4GHz RF transceiver embedded
  • Embeds internal RF matching circuit
  • RF link data rate: 250Kbps as specified in 802.15.4
  • Sensitivity: typical value -98dBm
  • Tx output power up to +8dBm
  • Single-pin antenna interface
  • RSSI monitoring
  • Benefits

  • Supports Zigbee Pro feature set
  • Thread support
  • Compliant with: Zigbee Home Automation, Zigbee Light Link, Zigbee Human Interface, and Zigbee RF4CE profiles
  • A range of reference applications for RF4CE remote controls and ZLL lighting systems to enable fast product developmen
  • Applications

  • Smart Home
  • Smart Lighting
  • Home/Building Automation
  • Smart Grid
  • Intelligent Logistics/Transportation/City
  • Consumer Electronics
  • Industrial Control
  • Health Care
  • Deliverables

  • RTL source code
  • SW source code
  • Technical Documents, and integration support
  • Reference code for Zigbee stack
  • Reference design, and SDK

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OverviewFeaturesRequest Datasheet

Description

A Complete 2.75G Cellular SoC (RF+Digital+SW) IP design from a Tier 1 semiconductor company that is in mass production in millions of phones world wide. Available as a complete chip design data base in source code &/or KGD/packaged part.

Features

Cellular Modem

  • GSM/GPRS/EDGE subsystem
  • GPRS Classes 1-12, Class B
  • HR/FR/EFR/AMR Vocoders
  • Dual core architecture
  • GSM/GPRS/EDGE subsystem
  • GPRS Classes 1-12, Class B
  • HR/FR/EFR/AMR Vocoders
  • RF Transceiver
  • Quad-band operation
  • Eliminates expensive VCTCXO
  • Significant margin for GCF
  • Integrated power management unit
  • Battery charging
  • Integrated LDOs
  • Deliverables

  • License protocol stack in image, object and source-code form to chipset providers, system integrators
  • Consultancy: strategy, customisation, porting, integration, product design, product co-design, and verification to licensees and others
  • Services: maintenance, support for test & validation, including field trials, conformance testing
  • Provision of terminal reference designs and modem modules through partnership

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OverviewFeaturesRequest Datasheet

Description

A GSM/GPRS/EDGE SW Protocol Stack IP that has been integrated with multiple basebands and shiped in 1bn phones and M2M modules world wide. Extensively field trialed, extremely modular, and independent of undelying hardware.

GSM/EGPRS handset stack has been designed to optimise:

  • Performance, incl high data rates, and low latency
  • Footprint: lowest memory use consistent with performance
  • Flexibility: rapid implementation with port to alternate base-band, RF chipsets and RTOS without main code changes; source code option
  • Debug, validation and field trials process: comprehensive graphical tools

All code is written in ANSI C and has been ported to 7 chipsets to date.

Sub-layers are mostly implemented as individual tasks (save for, e.g. RLC/MAC) communicatingthrough message queues. A description of the standard L1C, L2 & L3 stack is provided.

Features

  • Class B implementation multi-slot class 12 to 3GPP Release 1999 June 2007
  • GPRS PDP context. Packet services accessed via integrated TCP/ IP stack, or via PPP using an external PC or PDA.
  • Conforms to 3GPP Release ’99 / GCF-CC v3.35 bis (GCF-CC Version 3.35.0 dated 2009-07-06) and NAPRD.03 v5.0 bis (PTCRB NAPRD.03 v5.0) based on STAR-Let200Q M2M platform
  • Data rates to 80Kbps (GPRS); 400Kbps (EGPRS)
  • Quad-band support
  • PBCCH support
  • AT Command Interpreter implements 27.007 commands for GSM and GPRS; extended command set
  • SIM Interface supports Phase 1 & 2 cards
  • Layer 1
  • Type 1, multi-slot class 12
  • Simple primitive interface
  • Generic core design
  • Easily portable
  • Optimal power-saving
  • Internet Protocol (TCP/IP) provided by third party (Mentor Graphics)
  • Sub-Network Dependent Convergence Protocol (SNDCP)
  • Interfaces to AT command interpreter
  • Interfaces with IP directly or via PPP
  • Compression of TCP/IP headers (option)
  • GSM Short Message Service (SMS) GPRS Short Message Service (GSMS)
  • MO and MT messages sent / received over GPRS packet link
  • Circuit-Switched Data Option
  • Transparent & non-transparent up to 9.6 Kbits/sec (14.4 Kbps option)
  • Group 3 Fax Class 1
  • Portable to alternate RTOS through abstraction layer (GHDI, GSDI)
  • Deliverables

  • License protocol stack in image, object and source-code form to chipset providers, system integrators
  • Consultancy: strategy, customisation, porting, integration, product design, product co-design, and verification to licensees and others
  • Services: maintenance, support for test & validation, including field trials, conformance testing
  • Provision of terminal reference designs and modem modules through partnerships

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OverviewFeaturesRequest Datasheet

Description

NB-IoT, EC-GSM-IoT, LTE-M and CAT-M protocol stacks, along with service layers - oneM2M and OMA LWM2M - for next-generation M2M devices. Service Layer Platform supporting a service architecture including protocols, interoperability, test & conformance specification, and service layer interfaces.

The host-based sub-systems are available for licensing with integration/targetting and customisation services.

Available standard NAS variants for integration on existing AS

  • Cellular IoT
  • NB-IoT
  • EC-EGPRS

Features

  • Hand-code in 'C' for lowest footprint and latency
  • AS and L1-control as required
  • 'golden result' test data for acceptance and regression-test
  • Proven ability for system-wide defect-analysis and fast, reliable fixes
  • able to rapidly supply fixes to complex systems that avoid secondary problems and degradation of system integrity
  • Applications

  • License oneM2M/LWM2M layer (optional NB-IoT NAS)
  • License and integrate its oneM2M/LWM2M layer with customer’s existing NAS
  • Deliverables

  • C Source Code for software stack

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OverviewFeaturesRequest Datasheet

Description

UMTS Cellular Modem & SW Protocol Stack IP supporting GSM, GPRS, EDGE, WCDMA, HSPA functionality available for licencing.

Features

  • Modem: GSM/GPRS/EDGE/WCDMA/HSDPA
  • Band: Full Quad Band 850/900/1800/1900 Band I, II, IV, V, VIII support (TMO & AT&T qualification)
  • Release: EGPRS/DTM Class: 12/11 HSDPA R6 , DL/UL 7.2Mbps/384 kbps
  • Codec: HR, FR, EFR, AMR, AMR-WB speech
  • Encryption: A5/1, A5/3, GEA3, UEA1, UIA1
  • Feature: World-wide MB/US feature pack/DCXO support /SAIC
  • Audio
  • Ringtone: MIDI polyphony 128 voices
  • Codecs: Music stereo decoding in DSP MP3/AAC-LC/AAC+/eAAC+/WMA Encode: AAC stereo, SBC encode in DSP
  • Feature:3 analog Microphones + 2pdm
  • Integrated 1x 650mW (THD 1% @ 3.7V )
  • class-D amplifier
  • True Ground support
  • Video
  • Display: Up to WQVGA 16M colors
  • Interface VDE 8,9,16bits
  • Camera: 5Mpix YUV /JPEG
  • Interface CAM 8bits, CSI2
  • Decode: WQVGA 30fps MPEG4/H264/VC1/DivX
  • Encode: WQVGA 30fps MPEG4/H264
  • 2D GFX: OpenVG 1.1
  • Scalable Vector Graphics (SVG)
  • Adobe Flash Lite support
  • HW acceleration with perspective management
  • One shoot panorama, Video stabilization, Horizon leveling, Panoviewer
  • White box
  • RTL and Design Data Base
  • SW in Source code
  • Benefits

  • Silicon Proven
  • High volume Mass production, over 100mu world wide
  • Applications

  • Cellular Handset
  • M2M Modules
  • IoT
  • Deliverables

  • White box
  • RTL and Design Data Base
  • SW in Source code

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OverviewFeaturesRequest Datasheet

Description

The 8001 is a fully integrated single RF transceiver designed for Bluetooth, GPS and Beidou. The chip includes a fully integrated receiver path, transmit path, frequency synthesizer, programmable gain-controlled analog baseband and standard digital interface. It is compliant with Bluetooth 2.1+EDR , Bluetooth 3.0 and Bluetooth 4.0 with low power digital direct modulation TX path and linear IQ TX path. A integrated PA delivers up to + 4dBm (Class 2). For GNSS reception, the configurable core can receive the traditional GPS L1/Galileo E1 (1575.42MHz) as well as the GLONASS G1 (1603.5MHz), and Compass B1-1 (1561.098MHz) and B1-2 bands (1589.792MHz). A configurable analog baseband filter and versatile fractional PLL allows dual band reception of GPS/Galileo and Beidou or GPS/Galileo and GLONASS.

Features

  • Low-IF receiver with complex bandpass filter for Bluetooth RX
  • Low-Power digital modulation and IQ direct conversion TX architecture
  • Fast-lock PLL supporting Bluetooth frequency hopping
  • On-chip DC-offset cancellation and image rejection calibration circuitry
  • Integrated PA delivering up to +4dBm with connection for external PA
  • 70dB dynamic range RSSI
  • Fully integrated fractional-N synthesizer with low phase noise VCO
  • Supporting a wide range of low cost crystal from 10MHz-52MHz
  • IF gain settings can be digitally controlled by SPI or controlled by filtered analog voltage of PWM signal generated by the baseband.
  • 3-wire serial interface
  • Single 2.7V to 3.6V power supply with integrated 1.8V regulation
  • Low current consumption: 30/35mA for Bluetooth RX/TX and 20mA for GPS/Beidou
  • TSMC 180 CMOS
  • Small QFN-48 package
  • Deliverables

  • Pakaged Devices
  • KGD - Konown Good Die
  • GDSII - silicon IP
  • Ported to any fab/node

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OverviewFeaturesRequest Datasheet

Description

GSN GPS receiver is well suited for the Location Based Services exploiting market. in collaboration with leading DSP & CPU cores for the mobile, digital home and networking markets. The software based receiver presents a revolutionary cost-effective solution, addressing latest trends of miniaturization and low-power consumption.

Features

  • Eliminating extra silicon
  • GSN test equipment-GSN test simulators
  • Enabling any phone to nevigate indoor (Malls,Offices,tunnels)
  • Lower Battery consumption
  • Digitally controlled power saving mode for high power efficiency
  • Deliverables

  • Chip of KGD

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OverviewFeaturesRequest Datasheet

Description

The GPS L1/Galileo RF tuner is a highly integrated CMOS single-chip low-IF IC for GPS L1/Galileo reception. It features low power consumption and low number of external components. It includes LNA, down-conversion mixers, digitally adjustable automatic gain control circuitries, a complex positive pass filter with bandwidth calibration, IF programmable gain

amplifiers, 2-bits analog to digital converters, VCOs with a high resolution fractional-N PLL, digital controlled crystal oscillator (DCXO), and digital interface/control circuits.

Manufactured in CMOS technology and hosted in QFN32 package.

Features

  • 3-wire SPI (optional)
  • Fractional-N synthesizer ith fully integrated VCOs and parts of loop filter
  • Digital IF AGC with adjustable take-over points
  • Support various crystal frequencies (w/o writing internal register bits, 16.368MHz/19.2MHz can be used);
  • Can Offer fixed 16.368MHz sampling clock for different XTAL frequencies
  • Integrated DCXO eliminates the need for bulky and expensive VC-TCXO
  • On-chip automatic calibrations including AFC and LPF bandwidth
  • Digitally controlled power saving mode for high power efficiency
  • Integrated DC-Offset cancellation circuitry
  • Integrated band-adjustable image rejection filter
  • Digital adjustable channel select filter
  • Integrated 2-bits A/D to offer two bits digitized outputs
  • Applications

  • Dual-mode GPS/ Galileo receivers
  • Location- Based Services
  • Consumer Electronics
  • Portable Navigation Devices
  • Deliverables

    Chip of KGD

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OverviewFeaturesRequest Datasheet

Description

The design interfaces to an external Analog to Digital converter, which receives the analog signal from the external RF tuner. The included frequency correction can compensate for 500KHz frequency offsets for up to 20MHz channel bandwidth. The timing correction can correct mismatches as large as 50ppm.

The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to control its operation, and can be configured by an external processor via the AXI interface.

Features

  • LTE, Release 9 compliant CAT 0/1 PHY
  • Supports IF input
  • Flexible channel BW (1.4, 3, 5, 10, 15, 20) MHz
  • Modulation (QPSK, 16QAM, 64QAM)
  • PUSCH transmission:
  • Frequency hopping (Type 1, Type 2)
  • Data and control multiplexing (UL-SCH alone, UL-SCH multiplexed with UCI, UCI alone)
  • UCI (CQI, PMI, RI, ACK/NACK)
  • PUCCH transmission:
  • Format 1, Format 1a, Format 1b, Format 2, Format 2a, Format 2b
  • ACK/NACK
  • Random Access Preamble (Format 0, Format 1, Format 2, Format 3)
  • UL RS (PUSCH, PUCCH)
  • UL SRS (Transmission and hopping procedures for UL SRS in normal subframe)
  • CP length (Normal, Extended)
  • Primary Sequence Synchronization PSS (Primary Cell ID detection and initial timing synchronization)
  • Secondary Sequence Synchronization SSS (Secondary Cell ID detection and subframe synchronization)
  • CP Type detection (Normal, Extended)
  • PDCCH reception:
  • Blind decoding of PDCCH (UE specific search space, Common search space)
  • DCI parsing (all formats)
  • Monitored RNTI’s on PDCCH (All)
  • PDSCH reception:
  • TM 1 (Single antenna port 0)
  • DL RB allocation (Type 0, Type 1, Type 2 localized)
  • HARQ (supported)
  • Channel Estimation (Ver. 0) Flat fading only
  • Time tracking
  • Frequency tracking
  • Measurements (supported)
  • Parallel and Serial outputs
  • Register File port (Slave) to external processor
  • Applications

  • Machine to Machine communications
  • Wireless sensor networks
  • Deliverables

  • Synthesizable Verilog
  • System Model (Matlab) and documentation
  • Verilog Test Benches
  • Documentation
  • FPGA testing environment

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T2M's range of high quality pre-verified, analog/mixed-signal, RF, Digital and SW system solutions, are used as critical building blocks of communications, consumer and computer products including IoT, Wearables, cellular, tablet, M2M, RCU, set-top boxes, TVs, DVD players and PC chipsets. IPs can be modified to meet the customer's specific requirement be it fab/node porting or proprietary features.