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SoC White Box IPs

Hades Decoder IP

OverviewFeaturesRequest Datasheet

Description

The DENC is a high performance PAL/SECAM/NTSC digital encoder. It converts two 4:4:4 digital video streams into a standard analog baseband PAL/SECAM/NTSC signal and into RGB and YPrPb (also known as YUV) analog components. The DENC can handle interlaced mode (in all standards) and non-interlaced mode in PAL and NTSC. It can perform closed caption, CGMS, WSS, VPS and Teletext encoding and allows Macrovision TM 7.01/6.1 copy protection. Six analog output pins are available.    

Features

  • NTSC-M, PAL-BDGHI, N, M, Secam plus NTSC-4.43 encoding (optional pedestal in PAL and NTSC standards)
  • MacrovisionTM Rev7.01/Rev6.1 copy protection process in NTSC, PAL and Secam
  • Cross-color reduction by specific trap filtering on Luma within CVBS flow for both the CVBS (from main as well as aux) outputs
  • Closed captioning, CGMS, WSS, VPS encoding and TELETEXT encoding with included sequencer and shaping for both CVBS_MAIN and CVBS_AUX coming independently from main and aux video inputs
  • Digital frame sync input/output (ODDEVEN/VSYNC), programmable polarity and relative position.
  • Luma filtering with 2X oversampling and sin(y)/y correction
  • Chrominance filtering with 4X oversampling to either 1.1 MHz, 1.3 MHz, 1.6 MHz or 1.9 MHz (in PAL and NTSC) and chrominance filtering according to relevant Secam standards
  • Wide Chrominance bandwidth for RGB encoding (2.45 MHz IF CrCb are input at 6.75 MHz and 5.8 MHz IF CrCb are input at 13.5 MHz rate)
  • Saturation, contrast and brightness control of 4:4:4 aux and 4:4:4 main/ 4:2:2 from pad inputs
  • Programmable reset of color subcarrier phase (four modes)
  • Programmable access via parallel port
  • Programmable (4-bit) output levels RGB (-20% to +17%), C versus Y in CVBS and S-VHS (0 to +23.5%), PrPb (-25% to +22%), Y and CVBS (-25% to +22%) and C (-25% to +22%)
  • 4:4:4 input can be encoded on both RGB (YPrPb) and CVBS (S-VHS) outputs (programmable)
  • Autotest operation mode (on-chip color bar pattern 100/0/75/0)
  • Applications: satellite, cable and terrestrial digital TV decoders, multimedia terminals, DVD

Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell Documentation
  • Design Guide Verification Guide
  • Synthesis Guide

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OverviewFeaturesRequest Datasheet

Description

The Hardware Encoder Video Accelerator (HEVA), supports HEVC encoding low complexity with a flexible architecture targeting at least 1080p60 with minimal processing units and memory cuts, and up to 2160p120 with large number of units and large memory cuts.

Trade-off performance/area at design configuration

Reference cache size for 2160p30 at 350 MHz, 1 reference frame and bandwidth overhead of 100% for references i.e. 1.5 GBytes/sec (minimal is 1.2 GB/s)

Hardware interfaces

Host interface AXI3/AXI4 slave interface for the registers and command/status FIFO Memory interface AXI3/AXI4 Streaming interfaces to External DRAM Asynchronous AXI3/AXI4 128 bits interface Synchronous DMA arbiter and memory interface

Task sequencing modules

Manages communication and storage between processing modules Control the shared memories and caches between the TPU modules and TSU/MIF Defines the execution mode of the task processing units

Task processing modules

Perform the pixel and bit-stream processing under control of TCR/TSU The number of processing elements is defined at design configuration to sustain the required performance. A local reference cache is needed for performance for some processing units. 1476519495hevah-264

Features

  • Encoder acceleration

    • Performance up to 330 Mpixel/sec (2160p30 +1080p30)
    • HEVC Main support, Level 4.2 (2160p30)
    • H.264 High Profile Progressive, Level 5.1 (2160p30, 1080p120)
    • HEVC Sample Adaptive Offset in-loop deblocking
    • Full coding unit support (from CU 64x64 to CU 8x8, PU 4x4)
    • No restriction on MV range allowed (X<8192, Y<4096)
    • Slice support: single slice or number of CTB lines per slice
    • Slice level IT programmable

    Original input frame

    • Bottom/Right original padding on-the-fly
    • YUV 420 semi-planar: NV21

    Reference frame usage

    • Internal 2D frame format
    • Optional proprietary lossless compression on reconstructed/reference frames
    • Up to two reference frames
    • Generalized P/B frames for low delay encoding
    • GOP up to 8 frames hierarchical B-frames for random access encoding
    • Motion vector range not limited, trade-off bandwidth versus MV range up to the application programming and design configuration.
    • Programmable quality/performance trade-off

    Optional user defined input parameters

    • Deblocking slice parameters
    • User defined quantization scaling matrix tables
    • Chroma QP offsets
    • Region of interest input map table
    • Motion vector of Interest input map table

    Optional user report output

    • Motion vector field
    • with/without Basic picture analysis
    • Latency tolerance at design configuration

      Applications

    • HEVC & H264 Recorder & Transcoder, for NAS application for Set Top Box application Best in Class HEVC Transcoder .
    • HEVC & H264 Video monitoring on video surveillance sequences –
    • On outdoor, non-static sequences ~5 to ~10% of bit-rate reduction
    • On outdoor, static sequences ~10 to 20% of bit-rate reduction
    • On indoor & lowlight sequences ~10% of bit-rate reduction

    Deliverables

    • RTL Source Code
    • HDL based test bench and behavioral models
    • Test cases
    • Protocol checkers, bus watchers and performance monitors
    • Configurable synthesis shell
    • Documentation & Design Guide
    • Verification Guide
    • Synthesis Guide

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    4th generation H264 & VP8 encode IP Best in Class Video camcorder for low power applications. HW/SW configurable options helps to provide the high quality video encoding for both the boradcast and recording applications. It is suitable for low power applications.

    Low power ensured at the

    • Top clock-gating at IP level
    • Hierarchical Dynamic & automatic clock-gating
    • Register clock-gating
    • HVA IP – V 4.0 supports
    • H264 HP L5.1 - 4Kp30
    • VP8 1080p60
    • 2.05mm², 32nm FDSOI, 350MHz
    • 450Kbytes of eSRAM,
    • Optimal for DRAM bandwidth
    • 1165MB/s DDR 2768MB/s eSRAM HVA IP – V4.1 support
    • H264 HP L4.2 – 1080p60
    • VP8 1080p30
    • 1.58mm², 32nm FDSOI, 250MHz
    • 256Kbytes of eSRAM,
    • Optimal for DRAM bandwidth
    • 585MB/s DDR 1410MB/s eSRAM

    Features

    • HVA4.0 HP L5.1 - 4KP30 support
    • HVA4.1 HP L4.2 – 1080P60 support
    • Low power structure
    • OS Drivers - Android integration done, API fully configurable at frame level
    • Best in Class Encoder, configurable, scalable, customizable database for area & perf recovery
    • High DRAM latency resilience (sized for 2µs NoCs latency)
    • 256 client ID for SW, no VM support, HW command queue storing 8 client
    • Secure/non-secure support : 2 Dedicated command queue
    • Benefits

    • Production Proven
    • Tier 1 supplier
    • Integration support
    • Deliverables

    • Fully verified synthesizable RTL source code
    • RTL test bench
    • EVB for test and verification
    • Datasheet/Integration Guide/Verification Guide

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Low latency H264 encoder IP extracted from a production STB chip, with the functionality supported:

    Database1.0 & Package available

    • - H.264 HP L5.0 444 8/10/12bpp

    Low power structure

    • Top clock-gating at IP level
    • Hierarchical Dynamic & automatic clock-gating
    • Register clock-gating

    API

    - Fully configurable at frame level

    Features

    • H.264 HP L5.0 444 8/10/12bpp Encoder
    • Applications

    • SET top box video broadcast or Video survallence applications Video call/conf applications.
    • Deliverables

    • Fully verified synthesizable RTL source code
    • RTL source code
    • Simulation test bench with regression test suit
    • SW source code
    • Evaluation Board

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Best in Class Video encoder suitable for SET top box video broadcast or Video surveillance applications Video call/conf applications. HEVC HW Encoder, HEVA1.0 IP extracted from a production STB chip, with the following functionality:

    HEVC main support, 4KP30
    • Performance
    • 4Kp30
    • scalable for UHD & 8Ksupport

    Features

    • Configurable, scalable, customizable database for area & perf recovery from 3.5 to 4.5mm² 32nm
    • HEVC main 8bpp & H264 HPL4.2 HD60 and UHD30 HPL5.1 UHD30
    • High DRAM latency resilience (sized for 2µs NoCs latency)
    • Hierarchical & dynamical clock-gating design for ultra low power
    • Slice mode support for low latency application
    • Transform mode 16x16, 8x8 and 4x4, SAO, deblocking
    • LCU 64x64, no CU depth limit (configurable, up to 8x8)
    • 256 client ID for SW, 4VM support, HW command queue storing 8 client
    • Reference/Reconstruction Lossless compression for bandwidth reduction
    • Benefits

    • Full High Level Synthesis IP for flexibility, scalability, customization
    • Embedded Reference/Reconstruction Lossless compression for bandwidth reduction
    • Bandwidth System requirement for UHD30: 995MB/s DDR in average (Max load ~1194MB/s)
    • Bandwidth System requirement for HD60 : 480MB/s DDR in average (Max load ~560MB/s)
    • Embedded Cache with a configurable Search Window
    • +/- 256x128 pxls with the current cache configuration
    • RDOPT support
    • Embedded HW engine to evaluate coding choice according quality & perf-needs (patent)
    • HVS Physiological QP mechanism at CU level
    • Ultra-low CPU load
    • API Fully programmable at frame level
    • Low level driver available
    • Full Flexible Encoder API to interface Pre-Processing
    • Scene change & cut detection
    • Meta-data for frame pre-processing such as:
    • Adaptive Temporal & spatial noise reduction
    • Face detection, edge detection, logo insertion …
    • Bit Rate Controller externalization
    • Applications

    • Video monitoring
    • Video transcoding
    • Video call/conf applications
    • Deliverables

    • Configurable, scalable, customizable database for area & perf recovery from 3.5 to 4.5mm² 32nm
    • HEVC main 8bpp & H264 HPL4.2 HD60 and UHD30 HPL5.1 UHD30
    • High DRAM latency resilience (sized for 2µs NoCs latency)
    • Hierarchical & dynamical clock-gating design for ultra low power
    • Slice mode support for low latency application
    • Transform mode 16x16, 8x8 and 4x4, SAO, deblocking
    • LCU 64x64, no CU depth limit (configurable, up to 8x8)
    • 256 client ID for SW, 4VM support, HW command queue storing 8 client
    • Reference/Reconstruction Lossless compression for bandwidth reduction

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    OverviewFeaturesRequest Datasheet

    Description

    Hades decoder IP extracted from high volume STB SoC

    • •Real time HEVC scalable video decoder IP, leading 4K
    • •Picture quality tools (CEH)
    • •Full HLS + STHORM: Multi-core platform with configurable hardware accelerators (multi xP70 cores)
    • Versatile full HD video decoding

    Features

    • Real time HEVC scalable video decoder IP, leading 4K
    • Picture quality tools (CEH)
    • Full HLS + STHORM: Multi-core platform with configurable hardware accelerators (multi xP70 cores)
    • Benefits

    • Error correction capabilities - Robustness
    • Error concealment capabilities - Quality
    • Compliance to Allegro reference streams
    • Applications

    • Video monitoring
    • Video transcoding
    • Video call/conf applications
    • Deliverables

    • Fully verified synthesizable RTL source code
    • RTL test bench
    • SW source code
    • Datasheet/Integration Guide/Verification Guide
    • Evaluation Board

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

    Blitter display - 2D graphic and display Hardware accelerator with SW control for customization. It is fully Compliance with standard graphic libraries and buffer formats (DirectFB, Android HWComposer)

    Graphics blitter - Multi task and scalable, high performance, 2D graphic accelerator, SW control, Standard graphics software library acceleration (DirectFB, Wayland/Weston, Android Hardware composer). It has very low latency, QoS, Security & Virtualization support, Memory Bandwidth optimization.

    Ensures Source and destination windows all defined using an XY descriptor, with pixel accuracy whatever the format, from 1bpp to 32bpp.

    Most of these operators can be combined in a single BDisp pass.The BDisp works from memory to memory with a triple, dual or single source and one target.

    Features

    • Solid color fill of rectangular window & Solid color shade (fill + alpha blending)
    • Gradient fill of rectangular window (horizontal and Vertical gradient)
    • Color expansion (CLUT to true color) & correction (gamma, contrast, gain)
    • Rectangular clipping & Color Keying capability
    • 1-bit/8-bit clip mask bitmap for random shape clipping can be achieved in two passes
    • Plane mask feature available, Spatial De-Interlacing
    • Bi-endianness support, 90 degrees and multiples rotation support
    • 4:2:2 / 4:2:0 capabilities, as source format (2 buffer split format : field or frame Macro Block or Raster)
    • YUV capabilities, as source format (3 buffer split format)
    • 2D resize engine with high quality filtering, Horizontal and Vertical
    • VC1 “Range mapping / Range reduction” compensation algorithm
    • Fully programmable Matrix used for color space conversion, PSI, special effect
    • Programmable source/target scanning direction, both horizontally and vertically, in order to cope correctly with overlapping source and destination area
    • Adaptive Flicker filter from memory to memory (Shared between S1 and S2)
    • One source copy, with one or several operators enabled (color format conversion, 2Dscaling)
    • Two-source copy with alpha blending or logical operation between them
    • Deliverables

    • Verilog Source RTL Code plus Simulation Environment
    • C Source Code
    • Physical Design scripts - Synopsys synthesis
    • Hardware simulation test bench with regression test suit
    • Reference platform drivers

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    OverviewFeaturesRequest Datasheet

    Description

    The compositor sets-up display priorities and mixes real time SD, HD or Quad HD video planes from display processors and memory Flexible IP, configurable as per SoC need Made of one or several MIXER (HW composer) and GDP (versatile Graphics data DMA and processing) Available From 2.25 mm2 (Ultra HD 4K) to 0.46 mm2 (Full HD 2K) composistor

    Features

    • Flexible IP, configurable as per SoC need • Made of one or several MIXER (HW composer) and GDP (versatile Graphics data DMA and processing)
    • Next 4K mandatory features - HDR,2 pixels per clock cycle on GDP+, Capture 10b (same as DVP IP)
    • AXI4 migration
    • Quad HD compositor up to 4 mixers
    • The output color format is RGBsigned - up to 3 video layers & up to 8 GDP layers
    • The output color format is RGBsigned - up to 2 alpha plans & up to 2 capture pipelines
    • Deliverables

    • Verilog Source RTL Code plus Simulation Environment
    • C Source Code
    • Hardware simulation test bench with regression test suit
    • Reference platform drivers

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    OverviewFeaturesRequest Datasheet

    Description

    JPEG Decoder is a standard high-performance solution for still image and video decompression applications.

    At the rate of 30Mpps JPEG performs 12-22 times fast than conventional JPEG Decoders.

    Widely used across the Image and Video applications.

    Features

    • JPEG baseline decoder, 8 bits, 380MPel/s (4:2:0 format)
    • input formats - 4:4:4, 4:2:0, 4:2:2 and 4:0:0 additional input formats (4:1:1 and 4:2:1)
    • AXI4 migration
    • Color space conversion to RGB
    • Scaling in IDCT
    • Scanline decode, progressive decoding, IO suspension
    • Applications

    • Camera, Set Top Box, Video Broadcast, Smart phone
    • Deliverables

    • Fully verified synthesizable RTL source code
    • RTL test bench
    • Evaluation Board
    • Datasheet/Integration Guide/Verification Guide
    • User Guide

    Please fill in the form below

    OverviewFeaturesRequest Datasheet

    Description

      Image Signal Processing Algorithm IPs extracted from a Tier 1 Semiconductors production Application Processor. Functionality available is:

      Black offset removal

    • Channel offset - Pedestal removal
    • RSO - Pedestal removal with X/Y linear compensation
    • Rubik-offset - Bi-cubic grid-based spatially modulated offset correction
    • Defects and Noise reduction

    • Bruce - Simple Map based defect correction
    • Duster - Advanced Defect correction and Gaussian noise reduction
    • Norcos - Lumaand chromanoise reduction in YUV domain
    • Anok - Enhanced Norcoswith larger filter kernel
    • Scorpio - Green imbalance correction
    • Bayonet - Very high quality Bayer noise reduction to tackle with small pixels/low light challenge
    • Banok - Chroma noise reduction in Bayer domain
    • Color Shading correction

    • 4CH-AV - 4-channels gain compensation
    • Rubik-gain - 4-channels bi-cubic grid-based spatially modulated gain correction
    • Demosaic

    • 3x3Demo - Simple 3x3 low cost demosaic
    • Babylon - Directional demosaic
    • Mozart - Demosaicby frequency decomposition
    • AWB

    • DPN - Color selective auto-white balance
    • DPCN - DPN with higher color rejection
    • Auto-Exposure

    • AE - Multi-zone auto-expose algorithm
    • Auto-Focus

    • HCS - Single shot and continuous AF solution
    • HDR

    • Histom - Global Tone mapping algorithm
    • HawkEye - Multi frame merge algorithm with anti-ghosting
    • Torch - Local tone mapping
    • Color

    • Color Matrix - Crosstalk correction
    • Color Vibrancy - Smart color saturation
    • YUV transform - RGB 2 YUV transforms

      Scaler

    • GPScaler - Optimized upscale/downscale poly-phase filter
    • Sharpening

    • Peaking - Simple sharpening algorithm
    • Adsoc - Adaptive sharpening with Overshoot control
    • Norcossharpening - Adsocintegrated in Noise reduction IP
    • Linearization

    • FlexTF - Flexible linearization lut
    • Compression - 10?8, 10?7, 12?10 compression and decompression
    • Auto scene mode

    • ASM - Scene detection by DCT frequency analyzes
    • Detection

    • Face detection - Optimized detection of all faces in an image
    • Face identification - Recognition of a face
    • Smile detection - Detection of people smiling
    • Eye blink - Detection of eye blinking
    • Line detection - Line detection and segmentation for automotive market
    • Optical flo

    • FAST - Feature point detection
    • BRIEF - Feature point signature
    • Video stabilization

    • VS1.0 - Translational video stabilization
    • Jpeg

    • VC - 8 and 12 bits high speed Jpeg encoder
    • t - Bi-cubic grid-based spatially modulated offset correction

    Features

    • Black offset removal
    • Defects and Noise reduction
    • Color Shading correction
    • Demosaic
    • AWB
    • AAA - Automatic Exposure, Color Balance, Focus
    • HDR
    • Scaler
    • Sharpening
    • Linearization
    • Deliverables

    • Fully verified synthesizable RTL source code
    • RTL test bench
    • Evaluation Board
    • Datasheet/Integration Guide/Verification Guide
    • User Guide

    Please fill in the form below

    T2M's range of high quality pre-verified, analog/mixed-signal, RF, Digital and SW system solutions, are used as critical building blocks of communications, consumer and computer products including IoT, Wearables, cellular, tablet, M2M, RCU, set-top boxes, TVs, DVD players and PC chipsets. IPs can be modified to meet the customer's specific requirement be it fab/node porting or proprietary features.