9b-1.62Gsps I&Q ADC IP
A dual core I & Q Analog to Digital Converter based on the time interleaved SAR architecture.
The IP includes a power supply regulator (LDO), integrated references and digital compensation (for gain, offset and skew).
It works in a differential mode for analog input I & Q.
The output data are organized in 12x12b–buses clocked at 135MHz (Fs/12). Each bus gives the data coming from a specific sub-ADC. A data ready clock is provided at 135MHz (Fs/12).
The input buffers I & Q and the LDO are in G02.
The Core ADC and the Digital Compensation are in GO1.
- Maturity MAT05
- 9-bits DUAL-CORE I & Q SAR ADC
- Up to 1.62Gsps Sampling Rate
- Analog power supply for Input Buffer: from 1.7V to 2.75V (GO2 domain)
- Analog power supply for LDO: from 1.7V to 2.75V (GO2 domain)
- Digital power supply for Data Demux and Digital Compensation : 1.1V (GO1 domain)
- Input range: 1 Vpp differential for I&Q
- AC coupling input
- Input signal bandwidth: 100Hz to 600MHz
- Power down mode
- Data Ready output at 135MHz
- Technical Documents
- Design Guide