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SoC White Box IPs

Kasumi Cipher IP

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Description

The KSM1 core implements Kasumi encryption in compliance with the ETSI SAGE specification. It processes 64-bit blocks using 128-bit key. The basic core is very small (5,500 gates). Enhanced versions are available that support various cipher modes (ECB, CBC, OFB, CFB, CTR).

The design is fully synchronous and available in both source and netlist form. Test bench includes the Kasumi test vectors. The KSM1 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

Features

  • Encryption using the Kasumi Block Cipher Algorithm
  • Since all practical uses of Kasumi utilize only the encryption operation, decryption is not part of the core
  • High throughput: up to 3 Gbps in 65 nm process
  • Small size: from 5.5K ASIC gates, 289 Xilinx slices, 617 Altera ALUTs
  • Satisfies ETSI SAGE Kasumi specification and 3GPP TS 35.202
  • Processes 64-bit data blocks
  • Use 128-bit key
  • Completely self-contained: does not require external memory
  • Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables include test benches

Benefits

  • Technology        Max Freq.       Area               Throughput
  • TSMC65 G+       168 MHz       5,448 gates       1.3 Gbps
  • TSMC65 G+       365 MHz       7,675 gates       2.9 Gbps
  • Xilinx Virtex 5     100 MHz       289 slices        800 Mbps
  • Altera Stratix 3   120 MHz       616 AL
  • UT 960 Mbps

Applications

  • Secure mobile phone communications
  • 3GPP UMTS algorithms f8 and f9
  • A5/3 implementation
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Test vectors
  • Expected results
  • User Documentation
  • Netlist Licenses

  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Test vectors
  • Expected results
  • Tech Specs
  • Kasumi Cipher<>

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