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SoC White Box IPs

LXP2 Core IP

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Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. LXP2 implements the lossless compression /decompression algorithm and AES-XTS encryption /decryption on units of data (“blocks”).

Typical applications include enterprise data storage.

The design is fully synchronous and available in multiple configurations varying in bus widths and throughput.

LXP2 delivers 1-3 Gbps of throughput in both FPGA and ASIC implementations. The compression ratio greatly depends on the data and somewhat depends on the frames size; on typical file corpuses varies between 1.5 and 2.


  • Each frame is compressed and decompressed independently
  • Compatibility with public-domain LZ software implementations allows for interoperability
  • Parameterizable maximum block size (up to 16 megabytes)
  • Support for compression and decompression in a single core; dedicates compression and decompression versions are available
  • Back-to-back compression with no gaps between the frames
  • Applications

  • High-performance solid-state storage
  • Disk and tape storage systems
  • Deliverables

    HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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