MIPI D PHY IP
DescriptionThe D-PHY is a complete PHY, silicon-proven at multiple foundries. The D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI), Display Serial Interface (DSI) and Unified Protocol (UniPro) using the PHY Protocol Interface (PPI). MIPI D_PHY adheres to MIPI D-PHY Specification. The MIPI D-PHY along with MIPI CSI Transmitter or CSI Receiver or DSI Host or DSI Slave provides a complete solution for encoding or decoding MIPI data.
- Compliant with MIPI D-PHY Spec v0.9
- Programmable 1, 2 or 4 Data Lane Configuration.
- Supports High-Speed and Low-Power modes.
- Operate in continuous and non-continuous clock modes.
- Data Rate: 800 Mbps per lane on silicon (Spec mentions a max of 500 Mbps per lane) in HighSpeed mode and 10Mbps in Low-Power mode.
- Highly modular design
- Fully synchronous design
- Active low Asynchronous reset
- Verilog HDL
- FPGA: Xilinx ISE on Virtex 5
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
- MIPI D Phy