MIPI LLI IP
DescriptionLLI is a Low Latency Interface which is a point-to – point interconnect that allows two devices on separate chips to communicate as if a device attached to the remote chip is resident on the local chip.The connection between devices is at their respective interconnect level, eg: OCP,AMBA protocols, using memory mapped transactions. LLI is a bidirectional interface and is primarily targets low – latency cache refill transactions.LLI is a layered , transaction level protocol where Targets and Initiators on two linked chips exchange transactions without software intervention.Software is used only to configure and initialize LLI stack. MPHY is the PHY layer to transfer the symbols across chips connected through LLI protocol.Upto 12 lanes per direction can be used which would provide a very high speed serial data transfer across chips.
- Compliant with MIPI LLI V1.0, MIPI M-PHY spec v2.0.
- Lanes of each sub link (TX and RX) can be programmed separately up to 12lanes.
- M-PHY LS and HS data rates HS1X, HS2X supported.
- LLI can be configured as Master or Slave.
- LLI SVC TARGET, LLI BE_INITIATOR, LLIBE_TARGET, LLI LL INITIATOR, LLI LL TARGET are supported.
- Priority Arbitration based on Channel ID is handled across BE/LL in DL layer.
- Credit based channel implementation in DL.
- Test Mode supported – Media test mode, TPV, TPG which will enable TX/RX/ TX and RX conformance testing is supported.
- CRTPAT and CJTPAT test pattern generation and checking supported.
- MPHY configurable lanes of upto 12 per direction are supported.
- 10/20/40 bit MPHY interface data width supported.
- Support for LL and BE transfers.
- Support of NACK based error protection on MPHY link.
- Configurable marker0 insertion supported.
- Automatic save state to handle efficient power management supported.
- Highly modular design
- Fully synchronous design
- Configurable IP.
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts