MIPI M-PHY is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, memory, power management and Baseband to RFIC.
MIPI M-PHY Type I physical layer, HS Gear3 and PWM Gear7 compliant, designed in CMOS 28 nm technology for use in devices of mobile platforms.
The following components are included: One transmitter (TX) and two receivers (RX) where:
The transmitter includes 8B/10B encoder, parallel to serial converter and line driver. Each receiver includes line receiver, clock, and data recovery circuit for re-synchronizing received data, serial to parallel converter and 8B/10B decoder. The PLL provides multiple phases of high speed clocks for use both in M-TX and M-RX. It is a ring oscillator and charge pump based PLL.
Compensation and Bangap provides compensation codes for resistor calibration in the lanes. It also provides the various voltage and current references for use in the various lanes.