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SoC White Box IPs

MSP1 Core IP

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Description

Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message authentication, as well as header parsing and formatting operations on the transmitted and received packets. The basic MSP1 core is tuned for applications with a single Security Association (SA) and data rated100 Mbps to1 Gbps. Other options of the MSP1 cores are available supporting multiple SAs and data rates up to 100 Gbps.

The design is fully synchronous and available in both source and netlist form.

Features

    Small size combined with high performance:
  • Starting at less than 30K ASIC gates
  • 2 Gbps performance at 250 MHz
  • Self-contained, does not require external memory Optional statistic counters Very low latency
  • 12 clocks input-to-output (48 ns at 250 MHz clock)
  • Back-to-back packet processing
  • 64 bytes shortest packet
  • Supports encryption and decryption
  • Provides MACsec header parsing and modification:
  • Insertion and removal of the SecTag including the packet number (PN) and an optional SCI
  • RX packet validation
  • Insertion, validation and removal of the ICV
  • Replay protection based on the PN windowing
  • Includes key storage, lookup, and expansion
  • Key is provided on the input pins
  • Option with internal key storage with associative lookup is available
  • Support for Galois Counter Mode Encryption and authentication (GCM), Galois Message Authentication (GMAC)
  • Flow-through design
  • Test bench provided
  • Sample software for 802.1X-2010 (a.k.a. 802.1af, KEYsec, 802.1x-REV) key agreement (MKA) is provided
  • Deliverables
  • include test benches and optional NIST algorithm validation
  • Applications

  • WLAN 802.1ae MACsec
  • RFC 4869
  • Deliverables

    HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • User Documentation
  • Optional GCMVS NIST validation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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