PCI Gen4.0 16Gbps PHY IP
- T2M offers best in class highly configurable 16Gbps SerDes PHY, targeted for both enterprise and client application, complaint to PCie 4.0 specification 0.3. The PHY IP is designed to support a wide range of applications and can provides maximum throughput. The customer has a choice to customize it for lower data rates and upto 4 lanes configuration. This SerDes PHY integrated with partner company PCIe 4.0 controller to offer an complete integrated PCIe 4.0 hard IP.
- This SerDes supports wide range of industry Standards including PCIe 4.0, USB 3.1, XFI/SFI, JESD204B etc.
- PCIe_GEN4.0_PHY is multi-standard, high performance, low power, Single-Lane PCI Express Electrical PHY that can handle high level PCI Express protocol and its signalling needs. It is compliant to PCI Express Gen 4.0 base specifications 0.3 by PCI-SIG team and has features like clocking and clock & Data recovering, Serialization and De-Sterilization of Data, 128/130b 8/10b, data coding, Receiver detection and support high performance to Media Access Control layer device.
- T2M’s PCIe GEN 4.0 PHY uses 32/16bit Data PIPE interface. Its PIPE interface is a super set of PIPE interface for the PCI Express (PIPE) 4.0 specifications. It also supports latest lower power management’s states like L0s, L1, L1-sub-states and L2. PHY Gen 4.0 PHY IP is available in TSMC 28nm HPC/HPC+ process .
- Available SerDes PHY for the 10G/5G/2.5/10/16 Gbps
- Foundry 28,55 and 65nm
- Compliments to PCI Express base specification 4.0 and backward compatibility
- QUAD PCI Express 16/8/5/2.5Gbps per LANE and available in QUAD configuration
- Lowest latency in the Industry and Adaptive CTLE and 3 tap DEF receive equalization
- Configurable parallel data width of 8,16,32
- Single Supply voltage of 0.9V, Temp -40 to 125 deg C
- Tight control over termination resistor ( ~ 50 ohm) with on chip calibration
- Input reference clock of 100MHz to support 2.5G/5G/8G/16G data rates
- Support AC/DC coupled modes, Programmable VGA and Peak amp to support different cable applications
- Separate Amplitude path for Eye-diagram monitoring/DFE tap calibration/offset calibration
- CDR logic for better data alignment and locking , 3 taps TX equalization ( pre, main, post cursor ) , Programmable pre-emphasis
- Storage Area Networks (SAN)
- Solid State Drives (SSD)
- Networking Interface card
- Detailed specification of PCIe 16G PHY with All log files and signoff checklist agreed by customers
- Integration Guidelines ( Interface details, layout guidelines, power requirements)
- GDSII layout and Mapping file with LEF Abstract (Top level pin details, blockages and Boundary details)
- LVS compatible netlist for the LVS clean
- Verilog-A Model and IBIS mode ( optional)