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SoC White Box IPs

RC4 Core IP

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The RC4 core implements the RC4 stream cipher in compliance with the ARC4 specification. It produces the keystream that consists of 8-bit words using a key with the length up to 256 bits. The design is fully synchronous and available in both source and netlist form.

RC4 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.


  • Keystream generation using the RC4 algorithm
  • Small size: from 20K ASIC gates
  • Satisfies the ARC4 specification
  • Capability to save and restore internal state using a data bus with parameterized width.
  • Outputs keystream in 8-bit data words
  • Uses a key of up to 256 bits
  • Completely self-contained: does not require external memory
  • Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables include test benches
  • Applications

  • SSL/TLS accelerators
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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