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SoC White Box IPs


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The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites.
SSL1-AXI has a “lookaside” interface to the rest of system through two AXI interfaces:
  • AXI3/AXI4 slave for control
  • AXI3/AXI4 master for data transfer

The data stream through the control interface contains processing commands. Each command consists a pointer to the descriptor in the system memory. Descriptor contains source, destination, encryption context, processing length, and status.

The encryption context (keys, encryption state, etc.) as well as the packets are stored in the system memory attached to the AXI bus and are read and written via the master interface. The design is fully synchronous and is available in Verilog.


  • Throughput of 6-8 bits per clock (600-800 Mbps at 100 MHz)
  • Supports both encryption and decryption
  • Optional public-key RSA and ECC engines
  • Done signal for interrupting the CPU
  • Test bench provided


  • Embedded SSL/TLS applications


    HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • User Documentation
  • Netlist Licenses
  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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