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SoC White Box IPs

TSIO IP

OverviewFeaturesRequest Datasheet

The TSIO PHY interfaces with TSIO controller for TX and RX data communication as specified and certified by Nagra Vision. The control and status signals from TSIO PHY are also connected to the TSIO controller. It gets configuration from Fuse for enable or disable functionality and for configuring the minimum frequency of operation. The TSIO solution is 100% specification compliant and available with Transport stream front-end processor (STFE) and backend security processor along with TANGO processor.

 

Features

      • Generate the smart card interface frequency based on Fuse values and frequency configuration received from TSIO Controller.
      • Based on PAD control drives tri-states or differential zero on Data out and clock out pads.
      • Generates byte clock that would be used as TX and RX byte clocks
      • Generates TX Ready to indicate the TSIO controller to start streaming the data.
      • Serializes the data byte received from TSIO controller and sends on the TX line.
      • Generates the TX data and Clock out on differential pads meeting the electrical requirements.
      • Receives the data in on differential pads meeting the required electrical specifications.
      • Performs the data sampling alignment and continues tracking the phase of the clock with respect to data transitions.
      • Gives out the received data on a byte wide interface to the TSIO controller.
      • Generates the PLL lock and Receive clock lock status

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T2M's range of high quality pre-verified, analog/mixed-signal, RF, Digital and SW system solutions, are used as critical building blocks of communications, consumer and computer products including IoT, Wearables, cellular, tablet, M2M, RCU, set-top boxes, TVs, DVD players and PC chipsets. IPs can be modified to meet the customer's specific requirement be it fab/node porting or proprietary features.