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SoC White Box IPs

PCI X Controller IP

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Description

CPCI-X is a PCI-X compliant design scoped to provide a system interface to any networking application involving streaming data transfers. It basically focuses on the transfer of large chunks of data between the DMA unit of backend and the host memory adhering to PCI-X protocol (Rev 1.0) which is downward compatible with PCI protocol(Rev 2.2) and also on configuring the backend registers through memory accesses. The core provides a DMA arbitrator (optimized for two DMA controllers) and the initiatortarget pair to handle these transactions as per the PCI-X(Rev 1.0) protocol.

Features

  • Fully compliant with PCI-X protocol (Rev 1.0)
  • Posting for outbound memory writes
  • Basic power management supported in PCI-X mode
  • MSI capability
  • 64/32 addressing capability
  • 64/32 data transfer capability
  • Medium decode time supported for target
  • Flexible master-target interface that can be customized for varied data streaming applications
  • Fully synchronous design
  • PCI-X bus operation up to 133MHz
  • Good debugging support for erroneous transactions.
  • Applications

  • Good debugging support for erroneous transactions.
  • Highly modular design
  • Fully synchronous, technology-independent design
  • 64-bit wide internal data path
  • Clearly demarked clock domains
  • Deliverables

  • RTLcode
  • Detailed design document
  • Verification environment
  • Test cases
  • Synthesis environment guide
  • User Guide
  • Verification guide
  • Synthesis Guide

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