SoC White Box IPs

USB 3.0 Device Controller

OverviewFeaturesRequest Datasheet

Description

The DP/HDMI/DVI Receiver is a high-performance combo PHY with Display Port Receiver and HDMI Receiver. In DP mode, the receiver is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel. In addition to the standard DP1.1a HBR (2.7Gbps) and RBR (1.62Gbps) data rates, it can also support turbo mode (3.24Gbps) and HBRII (5.4Gbps) of DP1.2 standard. The IP does not support the optional FASTAUX and postcursor2 requirements of the DP1.2 standard. To facilitate lower test cost and improve test coverage, AUX channel include some testability features. In HDMI mode, the IP is HDMI 1.4b compliant. It can be customized process nodes from multiple foundries.

Features

  • Compliant with HDMI 1.4b & Display Port version 1.2 specification.
  • Input clock 135MHz for Display Port.
  • Supports upto HBRII (5.4Gbps/Ch) of DP 1.2 standard, 3D 1080p @60Hz.
  • Up to 21.6Gbps BitRate (4 X 5.4Gbps/Channel) in DP mode, 10.2Gbps (3 X 3.4Gbps/Channel) in HDMI mode.
  • 3.3V+5%, 1.8V+5% (Analog Supply), 1.0V+5% Analog Supply
  • Area and Process: Under NDA
  • Power On Consumption: Under NDA (Typ Process, HBR2 Display Port), Under NDA (Typ Process, 3.4Gbps/Ch HDMI).
  • At Speed BIST (Loop Back Test) incorporated.
  • Applications

  • HDMI/DP is the digital interface standard for connecting HD consumer electronics components.
  • Deliverables

  • Detailed specification with All log files and signoff checklist
  • Integration Guidelines ( Interface details, layout guidelines, power requirements)
  • GDSII layout and Mapping file with LEF Abstract (Top level pin details, blockages and Boundary details)
  • LVS compatible netlist for the LVS clean

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The HDMI 2.0 Compliant Phy supports up to 18gbps bit rate and enables to 4Kx2K resolution at 60Hz frame rate. It receives three streams (3x6Gbps) of 10-bit transition minimized data as input along with synchronous TMDS clock. It serializes and transmits them in differential form over three channels. The clock is also transmitted along with the data as a differential signal according to the specifications laid out in the Chapter “Electrical Characteristics” of the HDMI Standard specification of the Transmitter. This block consists of high speed serializer and output differential buffers along with the differential output pads and power supplies required by the block. The electrical layer can work over the TMDS clock range from 25MHz to 600MHz. It can be customized process nodes from multiple foundries.

Features

  • Compliant with HDMI 2.0 specification
  • Input clock (TMDS_CLK) from 10MHz to 600MHz range
  • Supports upto 4K2K @ 60 Hz, 3D 1080p @60Hz
  • Up to 18Gbps BitRate (3 X 6Gbps/Channel)
  • Pre-emphasis can be programmed as per the Board/Package parasitic’s
  • 1.8V+150mV (Analog Supply), 1.0V Digital Supply (0.85V to1.1V)
  • Area and process: Under NDA
  • Power On Consumption: 43.2mW (Typ Process, Typ Preemphasis at 6.0Gbps)
  • IOs integrated in the Digital and custom digital can be tested
  • At Speed BIST incorporated
  • In-built PRBS for Electrical Testing
  • Applications

  • HDMI/DP is the digital interface standard for connecting HD consumer electronics components.
  • Deliverables

  • Detailed specification with All log files and signoff checklist
  • Integration Guidelines ( Interface details, layout guidelines, power requirements)
  • GDSII layout and Mapping file with LEF Abstract (Top level pin details, blockages and Boundary details)
  • LVS compatible netlist for the LVS clean

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

HDMI receiver PHY (Physical layer) IP is single-port core which is fully compliant with HDMI 1.3a specification. This HDMI Rx PHY supports from 25MHz to 225MHz TMDS clock, and offers a simple implementation for system LSI for consumer electronics like HDTV. The HDMI Rx PHY performs most efficiently with HMDI receiver link IP core.

It is Silicon Proven in many Fab/Nodes including: 130/90/65/55/45/40nm.

Features

  • HDMI version 1.3a compliant receiver
  • Supports DTV from 480i to 1080i/p HD resolution
  • Supports 24bit, 30bit and 36bit color depth per pixel
  • Integrated cable terminator
  • Adaptive equalizer for cable
  • Adjustable analog characteristics
  • PLL band width
  • VCO gain
  • BGR voltage
  • Cable terminator resistance value
  • DLL digital filter characteristics
  • Integrated Audio PLL
  • 3.3V/2.5V/1.0V power supply
  • GLOBAL FOUNDRIES 65nm (C65G) proces
  • Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

HDMI receiver PHY (Physical layer) is a single-port IP core which is fully compliant with HDMI 1.4 specification. This HDMI RX PHY supports from 25MHz to 225MHz TMDS clock, and offers a simple implementation for system LSI for consumer electronics like HDTV. The HDMI receiver PHY performs most efficiently with HMDI receiver link IP core.
It is Silicon Proven in many Fab/Nodes including: 130/90/65/55/45/40nm.

Features

  • HDMI version 1.4 compliant receiver
  • Supports DTV from 480i to 1080i/p HD resolution
  • Supports 24bit, 30bit and 36bit color depth per pixel
  • Integrated cable terminator
  • Adaptive equalizer for cable
  • Adjustable analog characteristics
  • PLL band width
  • VCO gain
  • BGR voltage
  • Cable terminator resistance value
  • DLL digital filter characteristics
  • Integrated Audio PLL
  • 3.3V/2.5V/1.0V power supply
  • GLOBAL FOUNDRIES 65nm (C65G) process
  • Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

HDMI Transmitter Link IP Core supporting the standard of HDMI 1.3a which will be quickly implemented into SoC of consumers' product (HD-TV, AV receiver... etc.). The best performance, efficiency and characteristic of HDMI Rx IP can be realized when it is connected to HDMI Transmitter PHY IP. HDMI Tx IP can be customized to meet customer specific requirement.

Features

  • COMPLAINT WITH:
  • HDMI 1.3a
  • DVI 1.0
  • EIA/CEA-861D
  • HDCP 1.2
  • DIGITAL VIDEO OUTPUT
  • Digital TV resolution - 480i, 576i, 480p, 576p, 720p, 1080i, 1080p
  • PC resolution - VGA, XGA, SXGA, WSXGA, UXGA
  • RGB, YCbCr digital video format
  • 12bit RGB/YCbCr 4:4:4
  • 16/20/24bit YCbCr 4:2:2
  • 8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)
  • Programmable 2-way color space converter
  • YCbCr <-> RGB
  • Deep color supported up to 16bit per pixel
  • Support xvYCC
  • All Packets including Gamut Metadata Packet are receivable
  • DIGITAL AUDIO OUTPUT
  • Standard SPDIF for stereo or compressed audio up to 192KHz
  • PCM, Dolby Digital, DTS Digital Audio transmission through I2s up to 8 channel
  • IEC60958 or IEC61937 compatible
  • DSD (Direct Stream Digital) format for 1 bit Audio/SACD
  • High Bit Rate Compressed Audio (DTS HD master audio/Dolby True digital)
  • CONTENT PROTECTION
  • Built-in High-bandwidth Digital Content Protection (HDCP) encryption engine
  • Authenticate up to 2 receivers and repeaters with maximum cascade of 7
  • Support Advanced Cipher Mode
  • Support Enhanced Link Verification
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

HDMI receiver Link IP core which is fully compliant with HDMI 1.4a specification. This offers a simple implementation for system on chip (SOC) for consumer electronics like HD-TV, AV receiver. Its performs most efficiently with HMDI receiver PHY IP core. This HDMI core functions can be customized based on requirements.

Features

  • HDMI version 1.4a, HDCP revision 1.3 and DVI version 1.0 compliant receiver
  • Supports DTV from 480i to 1080i/p HD resolution, and PC from VGA to UXGA
  • Supports 3D video format specified in HDMI 1.4a specification
  • Programmable 2-way color space converter
  • Compliant with EIA/CEA-861D
  • Deep color supported up to 16bit per pixel.
  • xvYCC Enhanced Colorimetry
  • All packet reception including Gamut Metadata Packet
  • Supports RGB, YCbCr digital video output format including ITU.656
  • 24/30/36/48bit RGB/YCbCr 4:4:4
  • 16/20/24bit YCbCr 4:2:2
  • 8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)
  • 48 bit mode is not supported in 1080p
  • Supports standard SPDIF output for stereo or compressed audio up to 192KHz
  • Support PCM, Dolby digital, DTS digital audio output through 4bits I2S up to 8 channel
  • IEC60958 or IEC61937 compatible
  • 1bit audio format (Super Audio CD) output
  • High-bitrate compressed audio formats output
  • Slave I2C interface for DDC connection
  • Configuration registers programmable via synchronized parallel interface
  • Interface to external HDCP key storage

Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

HDMI Transmitter Link IP Core supporting the standard of HDMI 1.4b, with 16-bit deep color, 2.25 Gbps and 3D support which will be quickly implemented into SoC of consumers' product (HD-TV, AV receiver... etc.). The best performance, efficiency and characteristic of HDMI Rx IP can be realized when it is connected to HDMI Transmitter PHY IP. HDMI Tx IP can be customized to meet customer specific requirement.

Features

  • HDMI version 1.4a, HDCP revision 1.3 and DVI version 1.0 compliant receiver
  • Supports DTV from 480i to 1080i/p HD resolution, and PC from VGA to UXGA
  • Supports 3D video format specified in HDMI 1.4a specification
  • Programmable 2-way color space converter
  • Compliant with EIA/CEA-861D
  • Deep color supported up to 16bit per pixel.
  • xvYCC Enhanced Colorimetry
  • All packet reception including Gamut Metadata Packet
  • Supports RGB, YCbCr digital video output format including ITU.656
  • 24/30/36/48bit RGB/YCbCr 4:4:4
  • 16/20/24bit YCbCr 4:2:2
  • 8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)
  • 48 bit mode is not supported in 1080p
  • Supports standard SPDIF output for stereo or compressed audio up to 192KHz
  • Support PCM, Dolby digital, DTS digital audio output through 4bits I2S up to 8 channel
  • IEC60958 or IEC61937 compatible
  • 1bit audio format (Super Audio CD) output
  • High-bitrate compressed audio formats output
  • Slave I2C interface for DDC connection
  • Configuration registers programmable via synchronized parallel interface
  • Interface to external HDCP key storage
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.3 specification. The HDMI TX PHY supports from 25MHz to 250MHz pixel clock, and offers a simple implementation for system LSI for consumer electronics like DVD player/recorder and camcorder. It is Silicon Proven in many Fab/Nodes including: 130/90/65/55/45/40nm.

Features

  • HDMI version 1.3a compliant transmitter
  • Supports DTV from 480i to 1080i/p HD resolution
  • Supports 24bit, 30bit and 36bit color depth per pixel
  • Integrated cable terminator
  • Adaptive equalizer for cable
  • Adjustable analog characteristics
  • PLL band width
  • VCO gain
  • BGR voltage
  • Cable terminator resistance value
  • DLL digital filter characteristics
  • Integrated Audio PLL
  • 3.3V/2.5V/1.0V power supply
  • GLOBAL FOUNDRIES 65nm (C65G) process
  • Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.4 specification.HDMI transmitter PHY supports from 25MHz to 250MHz pixel clock, and offers a simple implementation for system LSI for consumer electronics like DVD player/recorder and camcorder.
It is Silicon Proven in many Fab/Nodes including: 130/90/65/55/45/40nm.

Features

  • HDMI version 1.4 compliant transmitter
  • Supports DTV from 480i to 1080i/p HD resolution
  • Supports 24bit, 30bit and 36bit color depth per pixel
  • Integrated cable terminator
  • Adaptive equalizer for cable
  • Adjustable analog characteristics
  • PLL band width
  • VCO gain
  • BGR voltage
  • Cable terminator resistance value
  • DLL digital filter characteristics
  • Integrated Audio PLL
  • 3.3V/2.5V/1.0V power supply
  • Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The HDMI Receiver IP provides an integrated functionality to interface with an HDMI compliant source and extract the corresponding video and audio signals. HDMI RX IP design provides a solution for organizing receiving data from link in accordance with DVI/HDMI1.1/HDMI1.2/HDMI1.3/HDMI1.4 with 3D interfaces and HDCP 1.4. IP is composed of HDMI v1.4 core and Physical Layer, in 65nmLP and 28nmLP.
Video: Full support for CEA 861 & HDMI 1.4b
Audio: All formats including Compressed, HBR & 1 bit audio
Data: Reception of standard
Supports Combo PHY (Display Port or HDMI) that de-serializes up to 3 gbps input. Maximum output speed is 240 MHz
Supports TMDS PHY (HDMI only input) that de-serializes up to 2.25 gbps input. Maximum output speed is 562.5 MHz
Link rate from 25MHz to 165MHz (DVI/HDMI1.1), up to 225MHz for HDMI1.3/1.3a and up to 297MHz for HDMI1.4
Option of 1:1, 2:1, 3:1 and 4:1 Mux
Cable equalizer and integrated line impedance matching per channel
Supports 3D video timing up to 1080P 60fr/Eye
RGB/YUV444/YUV422 color spaces; xv YCC support All possible color depth as HDMI 1.4
Automatic video/audio type detection and mute generation for excepted conditions
Up/Down color depth dithering at the video output
Automatic video screen blocking by programmed background color during video mute
Internal image format measurement block

Features

  • 4x I2S output for up to 8-channel PCM at 192 KHz or 61937-compressed stream
  • Configurable Output interface to SoC
  • Parallel video bus 24/30/36/48bit pixels, I2S audio out and 32 bit parallel audio output format, 1bit transmitter
  • Host CPU interface using STBus-T1 – Optional I2C, PBUS
  • I2C slaves for HDCP and DDC2Bi
  • Option on
  • o CEC 1.4 transceiver and message-level decode
  • o I2C Slave for MCCS with multiplexer to/from Any EDID channels
  • o Internal EDID I2C slave
  • External and internal EDID support on all ports
  • Crypto Core and NVS interface
  • Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

HDMI Receiver Link IP Core supporting the standard of HDMI 1.3a, which will be quickly implemented into SoC of consumers; product (HD-TV, AV receiver... etc.). The best performance, efficiency and characteristic of HDMI Receiver Link IP can be realized when it is connected to HDMI Receiver PHY IP. This HDMI Rx IP can be customized to meet customer specific requirement.

Features

    COMPLAINT WITH:
  • HDMI 1.3a
  • DVI 1.0
  • EIA/CEA-861D
  • HDCP 1.2
  • DIGITAL VIDEO OUTPUT
  • Digital TV resolution - 480i, 576i, 480p, 576p, 720p, 1080i, 1080p
  • PC resolution - VGA, XGA, SXGA, WSXGA, UXGA
  • RGB, YCbCr digital video format
  • 12bit RGB/YCbCr 4:4:4
  • 16/20/24bit YCbCr 4:2:2
  • 8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)
  • Programmable 2-way color space converter
  • YCbCr <-> RGB
  • Deep color supported up to 16bit per pixel
  • Support xvYCC
  • All Packets including Gamut Metadata Packet are receivable
  • DIGITAL AUDIO OUTPUT
  • Standard SPDIF for stereo or compressed audio up to 192KHz
  • PCM, Dolby Digital, DTS Digital Audio transmission through I2s up to 8 channel
  • IEC60958 or IEC61937 compatible
  • DSD (Direct Stream Digital) format for 1 bit Audio/SACD
  • High Bit Rate Compressed Audio (DTS HD master audio/Dolby True digital)
  • CONTENT PROTECTION
  • Built-in High-bandwidth Digital Content Protection (HDCP) encryption engine
  • Authenticate up to 2 receivers and repeaters with maximum cascade of 7
  • Support Advanced Cipher Mode
  • Support Enhanced Link Verification
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

  • The USB 2.0 Audio Design platform is a complete ,integrated solution,designed to be used in USB based Audio Devices such as speaker and microphones. You can use it in various applications,like portable flash memories, digital audio players, card readers and digital cameras.
  • This includes :
  • DUSB2 peripheral controller designed to support 12 Mb/S full speed and 480 Mb/S high speed serial data transmission rates.
  • DP8051XP ultra high performance ,speed optimized fully customizable 8051 8 bit microcontroller with built in debug IP core.
  • Audio device stack optimized software for DP8051XP 8bit CPU.
  • FPGA board with ready to use , pre programmed example USB stereo speakers applications.
  • Supports UTMI Transceiver Macrocell interface.

Features

  • Full complience with the USB 2.0 specifications
  • Full speed 12 Mbps operation
  • High speed 480 Mbps operation
  • Suspend and resume power management functions
  • 100% software compatible with 8051 industry standard
  • Upto 256 bytes of internal data memory
  • Up to 64k bytes of internal or external program Memory
  • User programmable program memory wait states solution for wide range of memories speed
  • User programmable External data memory wait state solution for wide range of memories speed
  • Fully syntheziable, static synchronous design with positive edge clocking and no internal tri states
  • Scan test ready

    Benefits

  • Fully Certified
  • Shipped in millions of products
  • Supper Low Power Consumption
  • Deliverables

  • Verilog/Vhdl Source Code
  • Modelsim automatic simulation macros
  • Audio device software stack source code
  • FPGA board with ready to use preprogrammed example application
  • Synthesis script
  • DataSheet

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

  • USB 3.0 controller core is a highly flexible and configurable design targeted for Device, Host and Hub implementations in desktop, mobile, networking and telecom applications.
  • The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption and silicon footprint. The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.
  • USB 3.0 controller core is a highly flexible and configurable design targeted for Device, Host and Hub implementations in desktop, mobile, networking and telecom applications.
  • The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption and silicon footprint. The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.
  • USB 3.0 Controller

Features

  • Compliant with USB3.0 Specification Version 1.0
  • Supports Interrupt / Bulk / Isochronous / Control Transfers
  • LFPS Support
  • Supports Aggressive Low Power Management
  • Configurable Core Frequency
  • Multiple Application Logic Interfaces
  • Pravega Native Packet Interface (PNPI) AXI / AHB Bus Interface
  • Optional DMA Controller
  • Configurable Datapath width on User Application Interface: 32, 64*, 128* bit
  • Configurable USB 3.0 PIPE Interface: 8, 16, 32 bit
  • Support for various Hardware and Software Configurability regarding Core characteristics
  • Configurable number of Configurations, Interfaces, Alternative Interfaces and endpoints
  • Support of control transfer processing by the core or optionally by an external processor.
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Software control for key features
  • Extensive clock gating support
  • Multiple Power Well Support
  • Deliverables

  • RTL Code
  • System Verilog based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Synthesis shell
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

USB 3.1 Host controller is a highly configurable core and implements the USB 3.1 Host functionality that can be interfaced with third party USB 3.1 PHY’s. USB3.1 Host controller core is part of USB3.0 family of cores named “Pravega”.

The Pravega Host Controller core is architected with an optional high performance DMA engine based on xHCI specification. The core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.

The Pravega Host Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.

The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.

The Controller also has a dedicated PHY Type-C connector Interface for identifying Type-C specific features such as cable orientation, ID function based on Configuration data channel etc.

Features

  • Compliant with xHCI and USB3.1 Specification Rev1.0
  • Implements Phy Logical/ Link / Protocol Layers.
  • Asynchronous clocking between Host Controller and Application logic
  • Supports Aggressive Low Power Management
  • Configurable system clock frequency
  • Optional Support for simultaneous Multiple IN transfers.
  • Configurable PIPE Interface: 8, 16, 32 bit.
  • Flexible User Application Logic
  • Supports Type2 Header Buffers
  • Supports SCD/LBPM LFPS Messages
  • Simple Register Interface for internal Register Access.
  • Optional support for Type-C connectors
  • Support for various Hardware and Software Configurability regarding Core characteristics.
  • Support Data, Video and Switch function
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Multiple loop backs for debug
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shellz

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The USB 3.0 Dual Mode controller is a highly configurable core and implements the USB 3.0 Host functionality or USB3 Device functionality selectable via a register or an external pin. The host/device core can be interfaced with third party USB 3.0 PHY's. The Dual mode controller supports Host functionality using high performance DMA engine based on xHCI specification exposing either an AHB or AXI interface. The host mode core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality. The pravega dual mode controller supports Device functionality which operates in a cut through mode exposing a native packet interface or exposes either an AHB or AXI interface and including a high performance proprietary DMA engine.
The Dual Mode Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications. The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.

Features

  • Host functionality is compliant with xHCI Rev1.0
  • Compliant with USB3.0 Specification Rev1.0
  • Compliant with USB Specification Rev 2.0
  • Compliant with USB2 Link Power Management
  • Supports Aggressive Low Power Management
  • Configurable core frequency: 125, 250, 500 Mhz.
  • Configurable PIPE Interface for USB3.0 PHY: 8,16, 32 bit.
  • Configurable USB2 PHY Interface : 8/16 bit UTMI,8-biot ULPI interface
  • Optional DMA engine for device mode functionality.
  • Optional endpoint zero processor block for processing standard requests for device mode functionality
  • Flexible User Application Logic
  • o Can be adapted by any SoC / OCB interface / offchip interconnects – such as AHB, AXI, PCIe
  • o Configurable Datawidth: 32, 64, 128 bit
  • o Optional native packet interface
  • Simple Register Interface for internal Register
  • Access – AHB Slave or GDA PBUS Interface
  • Pin or register bit to select between host/device
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Multiple loop backs for debug
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The USB 3.0 Hub controller is a highly configurable core and implements the USB 3.0 Hub functionality that can be interfaced with third party USB 3.0 PHY's. The Hub Controller core can be configured to support up to 15 downstream ports and the core supports all USB 3.0 defined power states. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB 3.0 PHY for aggressive power savings required for bus powered hubs.

The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and most importantly, the target technology. GDA solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications.

Features

  • Compliant with USB3.0 Specification Version 1.0
  • Configurable number of downstream ports
  • Configurable Core Frequency
  • Configurable Internal datapath width: 32, 64, or 128 bits
  • Compliant with standard USB 3.0 PHY Interface
  • Configurable PHY Interface width: 8, 16, or 32 bits
  • Efficient buffering scheme for forwarding packets through hub with minimal latency
  • Supports Bus and Self Powered Hub implementations
  • USB 3.0 low power states support
  • Support for various Hardware and Software Configurability regarding Core characteristics
  • Register Interface for internal Register Access
  • Support of Hardware and Software Configurability
  • Configurable Buffer sizes
  • Configurable shared buffers or per port buffers
  • Configurable number of Downstream Ports
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Software control for key features
  • Master and slave loop backs for debug
  • Aggressive power management
  • Deliverables

  • Design RTL Code
  • Verification Environment
  • Tests suites
  • Synthesis Environments & scripts
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The DUSB2 is a hardware implementation of a full/high-speed peripheral controller that interfaces to an UTMI bus transceiver. The DUSB2 contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic. The DUSB2 is designed to support 12 Mb/s "Full Speed" (FS) and 480 Mb/s "High Speed" (HS) serial data transmission rates. The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v 2.0. It is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.

Features

  • Full compliance with the USB 2.0 specification
  • Full-speed 12 Mbps operation
  • High-speed 480 Mbps operation
  • Supports UTMI Transceiver Macrocell Interface
  • Synchronous RAM interface for FIFOs
  • Suspend and resume power management functions
  • 100% software compatible with industry standard 8051
  • Up to 256 bytes of internal (on-chip) Data Memory
  • Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory
  • Up to 16M bytes of external (off-chip) Data Memory
  • User programmable Program Memory Wait States solution for wide range of memories speed
  • User programmable External Data Memory Wait States solution for wide range of memories speed
  • Allows operation from a wide range of CPU clock frequencies
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking
  • No internal tri-states
  • Lite design, small gate count and fast operation
  • Scan test ready
  • Applications

  • Portable flash memory device
  • Digital audio player
  • Card reader
  • Digital camera
  • Deliverables

  • Source code:
  • HDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Phone & email support

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

USB 3.0 OTG controller are designed for compliance with USB2.0 specification Revision 2.0 and all associated ECN’s and USB OTG EH 2 Revision 1.1a and all associated ECN’s. While operating in Host mode, based on configuration selected, it is compliant with xHCI, enabling standard Windows, Linux, Android drivers to be reused minimizing software development overheads and associated risks involved with custom bare metal driver solutions. Its Physical interface is compliant with USB 3.0 Pipe Specification v4.3 (for SS mode) and ULPI+ or 8/16 bits UTMI PLUS Level3 specification (for HS/FS/LS mode). The system interface is compliant with either AHB and/or AXI interface allowing easy integration. Optional custom bridges can be bundled as a service offering.
USB 3.0 OTG controller, while operating in device mode, can optionally include a our proprietary high performance DMA engine for moving USB payloads. The register interface of the DMA Engine is very simple allowing device side class specific function drivers to be implemented easily. Reference mass storage class device side function drivers are made available to all licensees. The same high performance DMA engine can be reused optionally for host mode operation, in which case custom bare metal drivers can be developed to manage the connected devices allowing highly optimized footprint for hardware and software. All buffering associated with the DMA Engine are configurable based on latency and performance requirements.

Features

  • USB 3.0 OTG Controller can be configured to support all types of USB transfers – Bulk, Interrupt and Isochronous. While operating in Device Mode it can be dynamically configured to support configurable number of endpoints, interfaces, alternate interfaces and configurations.
  • USB 3.0 OTG Controller can be configured to support any combinations of USB 3.0 interface speeds – LS(1.5 Mbps), FS (12.0 Mbps), HS (480 Mbps). Eg combinations are LS Only, FS Only, HS Only, LS and FS Only, FS and HS Only etc.
  • USB 3.0 OTG Controller has full support for all low power features of the USB Specification supporting Suspend, Remote Wakeup and USB 3.0 Link Management States - U1, U2, U3 and USB 2.0 Link Power Management states – L1, L2.
  • USB 3.0 OTG controller has full support for all USB 2.0 test modes features as well as USB 3.0 compliance and USB 3.0 loopback modes which is required for obtaining USB-IF certification.
  • USB 3.0 OTG Controller has full support for OTG features such as RSP, SRP, HNP and ADP along with software configurable options to turn on/off these features.
  • Applications

  • T2M provides been Silicon Proven USB Controllers for wide range of products such as Graphics Controller, Flash Storage Controllers, SATA Bridges with support for Bulk Streaming, Embedded Hosts, Docking Stations, Mobile Application Processors, Smart TV, Hubs.
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation and Synthesis Guide
  • FPGA Platform for Pre-Tape-out Validation
  • Reference Firmware

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The USB 3.0 Host controller is a highly configurable core and implements the USB 3.0 Host functionality that can be interfaced with third party USB 3.0 PHY's. The Host Controller core is architected with an optional high performance DMA engine based on xHCI specification. The core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.

The Host Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications. The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.

The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and most importantly, the target technology.

Features

  • Compliant with xHCI Rev1.0
  • Compliant with USB3.0 Specification Rev1.0
  • Implements Phy Logical/ Link / Protocol Layers.
  • Asynchronous clocking between Host Controller and Application logic
  • Supports Aggressive Low Power Management
  • Configurable core frequency: 125, 250, 500 Mhz.
  • Configurable PIPE Interface: 8, 16, 32 bit.
  • Flexible User Application Logic
  • Can be adapted by any SoC / OCB interface / offchip interconnects – such as AHB, AXI, PCIe
  • Configurable Datawidth: 32, 64, 128 bit.
  • Simple Register Interface for internal Register Access.
  • Support for various Hardware and Software Configurability regarding Core characteristics.
  • Optional USB2.0 Core for Backward Compatibility
  • Application Interface – AHB, AXI, PCIe
  • Configurable Buffer Sizes
  • xHCI Engine with configurable number of device slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Multiple loop backs for debug
  • Deliverables

  • Design RTL Code
  • Verification Environment
  • Tests suites
  • Synthesis Environments & scripts
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

USB 3.1 Hub controller is a highly configurable core and implements the USB 3.1 Hub functionality that can be interfaced with third party USB 3.1PHY’s. USB3.1 Hub controller core is part of USB3.0 family of cores named “Pravega”. The core leverages GDA’s design expertise from its high speed interconnect family of IP’s including PCI Express, Serial RapidIO and Hypertransport.

The Pravega Hub Controller core can be configured to support upto 15 downstream ports. The Pravega Hub Controller core supports all defined USB 3.1 power states. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB 3.1 PHY for aggressive power savings required for bus powered hubs.

The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.

Features

  • Compliant with USB3.1 Specification Version 1.
  • Configurable number of downstream ports
  • Configurable Core Frequency
  • Configurable Internal datapath width: 32, 64, or 128 bits
  • Compliant with standard USB 3.1 PHY Interface
  • Configurable PHY Interface width: 8, 16, or 32 bits
  • Efficient buffering scheme for forwarding packets through hub with minimal latency
  • Supports Bus and Self Powered Hub implementations
  • Supports PTM.
  • Supports SCD/LBPM LFPS messages.
  • Supports Type 2 Header buffers.
  • Supports TP reordeirng.
  • USB 3.1 low power states support
  • Support for various Hardware and
  • Software Configurability regarding Core characteristics
  • Register Interface for internal Register Access
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Software control for key features
  • Master and slave loop backs for debug
  • Aggressive power management
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

USB 3.1 Device controller is a highly configurable core and implements the USB 3.1 Device functionality that can be interfaced with third party USB 3.1 PHY’s. USB3.1 Device controller core is part of USB3.0 family of cores named “Pravega”.

The Pravega Device Controller core is architected with an high performance DMA engine based on USB3.1 specification.The Pravega Device Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.

The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.

The Controller also has a dedicated PHY Type-C connector Interface for identifying Type-C specific features such as cable orientation, ID function based on Configuration data channel etc.

Features

  • Compliant with USB3.1 Specification Rev1.0
  • Implements Phy Logical/ Link / Protocol Layers.
  • Supports Aggressive Low Power Management
  • Configurable system clock frequency
  • Support simultaneous Multiple IN transfers.
  • Implements PTM.
  • Supports Bulk Streaming.
  • Configurable PIPE Interface: 8, 16, 32 bit.
  • Flexible User Application Logic whichincludes Optional Support for EP0 Processer for processing control transfers
  • Optional proprietary DMA Controller in Application Layer.
  • Optional support for Type-C connectors
  • Supports Type2 Header Buffers
  • Supports SCD/LBPM LFPS Messages
  • Simple Register Interface for internal Register Access.
  • Support for various Hardware and Software Configurability regarding Core characteristics.
  • Support Data, Video and Switch
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Deliverables

  • Configurable RTL Code
  • Configurable synthesis shellz
  • Protocol checkers, bus watchers and performance monitors
  • Test cases
  • HDL based test bench and behavioral models

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

USB 2.0 Host controller is a highly configurable core and implements the USB 2.0 Host functionality that can be interfaced with third party USB 2.0 PHY’s. USB2.0 Host controller core is part of USB3.0 family of cores.
Host Controller core is architected with an high performance DMA engine based on xHCI specification. The core can be configured to support full-fledged USB 2.0 host controller based higher performance xHCI specification for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.
The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI,AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.
The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.
  • Configurable Options
  • Optional USB3.0 Core for Superspeed Support
  • Application Interface – AHB, AXI, PCIe
  • Configurable Buffer Sizes
  • xHCI Engine with configurable number of device slots, interrupters, root hub ports, configurable scratchpad support, optional support for host initiated stream data movement and optional debug capability etc
  • Also available - USB 2.0 Audio , USB 2.0 HID,USB 2.0 OTG Controller and USB2.0 Device Controller and Device

Features

  • Compliant with xHCI Rev1.0
  • Compliant with USB Specification Rev 2.0
  • Supports HS/FS/LS mode of operation.
  • Asynchronous clocking between Host Controller and Application logic.
  • Supports Aggressive Low Power Management
  • Configurable PHY Interface: 8/16 UTMI, ULPI.
  • Flexible User Application Logic
  • Can be adapted by any SoC / OCBinterface / offchip interconnects – such asAHB, AXI, PCIe
  • Configurable Datawidth: 32, 64, 128 bit.
  • Simple Register Interface for internal Register Access.
  • Support for various Hardware and Software Configurability regarding Core characteristics.
  • Easy migration path for Superspeed Support
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Applications

  • Human Interface Devices like keyboards,
  • mousses or game peripherals
  • Mass Storage devices like flash disks, mp3 or mp4 players
  • GPS navigation systems
  • Digital Cameras
  • Cellular phones
  • Audio devices like microphones and speakers
  • Printers
  • Scanners
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

T2M a leading provider of High Speed Serial Interface IPs solutions, provides 10Gbps SerDes in leading 28nm process which supports USB 3.1 PMA specification. The transceiver is integrated with low jitter 10GHz PLL which offers excellent phase noise margin. This IP also supports 5 Gbps USB 3.0 standard.
Technology Option
  • GF 28SLP
  • TSMC 65G
  • TSMC 28HPC (0.9V)
Power Management
  • 4 Defined Power States
  • Active Current Sensing
  • Maximum Power Level Enumeration

Features

  • USB 3.1 with backward compatibility (USB 3.0) Meeting all specs of USB 3.1
  • Parallel data width 8 Bits with QUAD configuration ( 4 TX and 4RX ), Single Lane Configuration (1 Tx, 1Rx)
  • Support Signal loss & receiver detection
  • Programmable 3 tap & de-emphasis, Support 1m cable
  • Optimized Metal Stakes for Lower NRE expense ( 6020+LB )
  • 1.0V supply to support -40 to 125 deg.C
  • CDR logic for better data alignment and locking, Complaint with PIPE 4.2
  • High speed low jitter 10GHz PLL
  • Applications

  • Storage
  • Switches and Bridge
  • Surveillance Camera
  • Digital Still Camera
  • 4K/8K TV

    Deliverables

  • GDSII layout and layer map files with Abstract with size and pin locations (lef)
  • verilog-a, CDL, encrypted Spectra netlist and Verification reports and environment
  • Test cases, bring-up plans, coverage Reports , Timing views (.lib)
  • Synthesis environment/Scripts , System level simulation model for channel simulations

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII in cooperation with external PHY device enables network functionality in design. It is capable to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The Core is able to work with wide range of processors: 8, 16 and 32 bit data bus, either little or big endian byte order format. The DMAC-RMII provides static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in variety of process technologies. This Core strictly conforms to the IEEE 802.3 standard.

Features

  • Conforms to IEEE 802.3-2002 specification
  • Configurable width CPU interface with little or big endianess:
  • 8-bit
  • 16-bit
  • 32-bit
  • Simple interface allows easy connection to CPU
  • Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories
  • Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
  • Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers
  • Supports full and half duplex operation at 10 Mbps or 100 Mbps
  • CRC-32 algorithm:
  • calculates the FCS nibble at a time
  • automatic FCS generation and checking
  • able to capture frames with CRC errors if required
  • Dynamic PHY configuration by STA management interface
  • Early receive and transmit interrupts to increase data throughput
  • Programmable MAC address
  • Promiscuous mode support
  • Allows operation from a wide range of input bus clock frequencies
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking
  • No internal tri-states
  • Lite design, small gate count and fast operation
  • Scan test ready
  • Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Phone & email support

Please fill in the form below

OverviewFeaturesRequest Datasheet

Please fill in the form below

OverviewFeaturesRequest Datasheet

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels. It also selects the correct destination for each data packet (Bayer input of ISP, RGB/YUV input of ISP, Memory). The IP reorders up to 4 x 1.5 Gbps data lanes, separates sensor clock of CSI-2 Core from DPHY byte clock. IP is able to store in memory all CSI2 datatype and to process rawbayer, compressed rawbayer, yuv pixel reconstruction for on the fly ISP processing. It also performs ECC/CRC check & correction. CSI-2 Receiver IP supports Virtual Channel and Datatype selection. It supports continuous and gated clock configurations.
Main HW modules are -
  • 1. CSI2RX Front handles:
  • o DPHY lanes swapping
  • o Sensor clock isolation
  • 2. CSI2RX Protocol module handles:
  • o CSI2 Protocol (including ECC, CRC, Virtual channel & Data types)
  • o Start/End of frame, programmable & truncated frame interruptions
  • 3. SMIARX module handles:
  • o SMIA ISL lines support
  • o Frame generation on pixel output based on programmed frame format description
  • 4. Output Control module handles:
  • o Virtual Channel / Data type de-interleaving
  • o Command of Depacker module
  • 5. Depacker module handles:
  • o Control of multipurpose FIFO
  • o Byte to pixel conversion
  • o ISL specific depacking
Main interfaces are -
  • 1. APB 32 bits slave interface for register accesses
  • 2. CSI2 DPHY interfaces: Three DPHY interfaces up to 4 Data Lanes
  • 3.Pixel outputs: Two exclusive pixel outputs (1 for RAW Bayer data and 1 for RGB & YUV).
  • 4. Packed outputs: Two packed outputs. These outputs will use srdy/drdy protocol to provide 64 bits packed in bytes.
  • 5.ISL output: One ISL output for each depacker. This output will use srdy/drdy protocol to provide 64 bits packed ISL lines.
  • 6. Memory interface: One memory control interface.

Features

  • Compliant with MIPI Alliance Specification for Camera Serial Interface 2 v1.01 and SMIA 1.0 Part 1 v1.0
  • Support of CSI2 interface up to maximum 4*1.5 Gbps
  • 1 to 3 DPHY interfaces up to 4 data lanes each, compliant with MIPI D-PHY PPI
  • Full byte to pixel conversion
  • Automatic start of frame synchronization when enabled
  • Packed outputs: any format packed on 64 bits
  • Pixel outputs -
  • RAW bayer (6, 7, 8, 10, 12, 14 bpp)
  • YUV422 interleaved raster (8, 10 bpp)
  • RGB888
  • Benefits

  • Configurable DPHY Interface number
  • Configurable Data Lane number (independent for each DPHY I/F)
  • Virtual Channel / Data type de-interleaving
  • Protocol error detection
  • SMIA Protocol handling
  • Byte to pixel conversion
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

LLI is a Low Latency Interface which is a point-to – point interconnect that allows two devices on separate chips to communicate as if a device attached to the remote chip is resident on the local chip.The connection between devices is at their respective interconnect level, eg: OCP,AMBA protocols, using memory mapped transactions. LLI is a bidirectional interface and is primarily targets low – latency cache refill transactions.LLI is a layered , transaction level protocol where Targets and Initiators on two linked chips exchange transactions without software intervention.Software is used only to configure and initialize LLI stack. MPHY is the PHY layer to transfer the symbols across chips connected through LLI protocol.Upto 12 lanes per direction can be used which would provide a very high speed serial data transfer across chips.

Features

  • Compliant with MIPI LLI V1.0, MIPI M-PHY spec v2.0.
  • Lanes of each sub link (TX and RX) can be programmed separately up to 12lanes.
  • M-PHY LS and HS data rates HS1X, HS2X supported.
  • LLI can be configured as Master or Slave.
  • LLI SVC TARGET, LLI BE_INITIATOR, LLIBE_TARGET, LLI LL INITIATOR, LLI LL TARGET are supported.
  • Priority Arbitration based on Channel ID is handled across BE/LL in DL layer.
  • Credit based channel implementation in DL.
  • Test Mode supported – Media test mode, TPV, TPG which will enable TX/RX/ TX and RX conformance testing is supported.
  • CRTPAT and CJTPAT test pattern generation and checking supported.
  • MPHY configurable lanes of upto 12 per direction are supported.
  • 10/20/40 bit MPHY interface data width supported.
  • Support for LL and BE transfers.
  • Support of NACK based error protection on MPHY link.
  • Configurable marker0 insertion supported.
  • Automatic save state to handle efficient power management supported.
  • Benefits

  • Highly modular design
  • Fully synchronous design
  • Configurable IP.
  • Deliverables

  • RTL code
  • Detailed design document
  • Verification environment
  • Test cases
  • Synthesis environment/scripts

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

UniPro (Unified Protocol) is a layered protocol defined by MIPI Alliance for interconnecting devices and components within a mobile device. UniPro enables the components of a device to utilize MIPI PHY layer, like MPHY to communicate and exchange data to devices on the other side of MIPI lanes. UniPro supports a wide range of device applications like application processor, camera controller, display controllers, storage controllers like UFS, memory (RAM) controllers etc.
The MIPI UniPro is designed to be PHY agnostic and can support a wide range of multiple applications simultaneously in the application layer. The MIPI UniPro along with our Application solutions like CSI-3 or UFS and Our MPHY forms a complete solution to your needs.

Features

  • Compliant with MIPI UniPro Standard V1.41.00 and MPHY standard 2.0
  • Programmable 1, 2, or 4 data lanes
  • M-PHY HS data rates HS-G1,G2,G3 A/B and PWM data rates PWM-G1 to PWM-G7
  • End to End flow control.
  • Supports all traffic classes.
  • Supports preemption of high priority frames.
  • Supports maximum of 32 CPorts.
  • Employs Round Robin arbitration across CPorts.
  • Supports group acknowledgement of maximum 16 frames per traffic class.
  • Supports retransmission of frames.
  • Configurable buffer spaces.
  • Supports CSD, CSV.
  • Supports UniPro Test Feature.
  • TMPI Support.
  • Benefits

  • Highly Modular and scalable design
  • Active-low
  • Asynchronous reset
  • Deliverables

  • RTL Code
  • Verification Environment
  • Test Cases
  • Synthesis Environment and scripts
  • Detailed Datasheet, Design Guide, Verification Guide and Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The MIPI MDDI Unified Solution is compliant with the MIPI Alliance Standard for D-PHY version 1.0 and the VESA Mobile Display Digital Interface Version 1.2 specification. It consists of 4 lanes, 1 Clock/Strobe lane, 1 bidirectional data lane and 2 unidirectional data lanes, which makes it suitable for display interface applications. The MDDI and MIPI blocks share the same signal and supply pins. The on-chip receive termination can be used for both MDDI and MIPI. The termination resistors can be calibrated to minimize variations. Once the Display module is qualified it can be used for both MIPI and MDDI resulting in faster time to market and in area and cost savings.

Features

Configurable as MIPI Slave or MDDI Client Complies with MIPI Alliance Specification for D-PHY V1.0 and VESA MDDI V1.2 Consists of 1 Clock/Strobe lane, 1 bidirectional data lane and 2 unidirectional data lanes Supports both high speed and low-power modes Operates up to 800 Mbps/lane in high speed mode De-Serializers included Optimized for minimal power dissipation & footprint Programmable integrated receive termination Programmable reverse MDDI TX amplitude and CMV(Common Mode Voltage) Built-in testability to enable for full speed production test Silicon Proven in multiple Fabs/Nodes

Deliverables

RTL code Detailed design document Verification environment Test cases Synthesis environment/script

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

MIPI M-PHY is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, memory, power management and Baseband to RFIC. MIPI M-PHY Type I physical layer, HS Gear3 and PWM Gear7 compliant, designed in CMOS 28 nm technology for use in devices of mobile platforms.
The following components are included: One transmitter (TX) and two receivers (RX) where: The transmitter includes 8B/10B encoder, parallel to serial converter and line driver. Each receiver includes line receiver, clock, and data recovery circuit for re-synchronizing received data, serial to parallel converter and 8B/10B decoder. The PLL provides multiple phases of high speed clocks for use both in M-TX and M-RX. It is a ring oscillator and charge pump based PLL. Compensation and Bangap provides compensation codes for resistor calibration in the lanes. It also provides the various voltage and current references for use in the various lanes.

Features

  • Input clock frequency: 19.2 MHz/26 MHz/38.4 MHz/52 MHz @ 1.8 V.
  • Refclk phase noise quality: integrated SSB phase noise of -66 dBc from 10 KHz to 10 MHz (noise assumed uniformly distributed in the entire band).
  • High Speed (HS) mode support upto Gear3 for both rate series (A and B), both for TX and RX. In HS mode, supports an intermediate bit rate of 3.952 Gbps (with 26 MHz refclk only).
  • PWM mode support upto Gear7, both for TX and RX.
  • Supports Sleep Mode, Hibernate Mode, Stall Mode and the various Burst states, that is,Type I state machine including the LINE-CFG states.
  • Supports terminated and unterminated operations.
  • Supports small amplitude and large amplitude.
  • Includes Built in PHY Test mode (combination of TX and RX) with loopback (digital loopback only).
  • Phy Protocol Interface is compliant to mipi_MPHY_specification_v1-4 with 40 bit/ 20 bit /10 bit inter face options.
  • Macrocell includes clock multiplication unit (PLL) for high speed clock generation.
  • Macrocell DFT control is IEEE-1500 compliant.
  • Silicon Proven in multiple Fabs/Nodes
  • Benefits

  • 28 nm CMOS technology
  • Includes 1 transmitter and 2 receivers
  • Input clock frequency: 19.2 MHz / 26 MHz /
  • 38.4 MHz / 52 MHz @ 1.8 V
  • Applications

  • Display
  • Camera
  • Audio & video
  • Memory
  • Power management and Baseband to RFIC
  • Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • GDSII ported to required process node
  • Physical Design scripts
  • Hardware simulation test bench with regression test suit
  • Comprehensive documentation and training
  • Tech Specs

  • 28 nm CMOS technology
  • Includes 1 transmitter and 2 receivers
  • Input clock frequency: 19.2 MHz / 26 MHz /
  • 38.4 MHz / 52 MHz @ 1.8 V

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

I3C interface is a fast, low cost, low power, two wire digital interface for sensors in mobile wireless products. Our I3C supports several communication formats all sharing a two wire interface - SDA and SCL. SDA is a bidirectional data pin while SCL can be either a clock pin or a data pin while in HDR mode. The type of communication supported by I3C
I2C-like communication with SCL clock speed up to 12.5 MHz , MIPI-defined transmissions that allow the master to communicate to one or all slaves on the bus. HDR mode using ternary number symbols to achieve two data transmissions per equivalent clock cycle. A subset of I2C communication to legacy I2C slaves, if present on the bus. Slave initiated request to master, e.g. In-band interrupt, address request.

Features

  • Compliant with the MIPI Alliance
  • Draft Specification for I3C Version 0.5 Revision 1
  • I3C Master Features
  • Supports all modes of Master – SDR, HDR and HDR-DDR,I2C Modes
  • Can be configured to work as secondary master also.
  • Dynamic addressing assignment capability
  • Support for slave generated in band interrupts.
  • Memory for retaining bus device addresses.
  • I3C Slave Features
  • Supports I3C slave configuration – HDR-DDR Slave, SDR Only Slave.
  • Common Slave IP can be instantiated many times to have multiple slaves on the I3C bus.
  • Dynamic address complaint.
  • Supports/Tolerate I3C global command codes.
  • Master Interface for system access : APB. Optionally AXI.
  • Slave Interface for Register access : APB
  • Configurable FIFOs
  • Benefits

  • I3C Master Can be configured to work as secondary master.
  • I3C Slave configuration – HDRDDR Slave, SDR only Slave.
  • System Access: APB or AXI
  • Configurable FIFO’s
  • Highly modular and configurable design
  • Supports both sync and async reset
  • Software control for key features
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The MIPI SoundWire is an interface specification that enables bi-directional digital Audio communication between a Master and one or more slave devices and among slave devices. It is optimized for mobile and Mobile inspired systems. It can co-exist with MIPI-Compliant and non-MIPI-Compliant devices.
MIPI SoundWire is low-complex, low-power, low-latency interface that supports multichannel data. Being low gate count enables it to be adopted it into smaller components like microphones and amplifiers.
L&T’s SoundWire Master is used in any master controllers like Amplifiers or processors to transfer or receive audio data from one of the SoundWire slaves, like the one connected to a microphone or a speaker. Likewise L&T’s SoundWire Slave is a full SoundWire standard compliant slave that can do a slave to slave communication according to the device component connected to it.

Features

  • Compliant with MIPI SoundWire Standard 0.9r05
  • SoundWire Host can support up to 11 Slaves.
  • Up to 8 Data Lanes supported
  • Slave-to-Slave transport supported
  • Modified-NRZI Data Encoding.
  • Special internal register space for each devices
  • Optional Monitor Interface
  • Optional APB/AXI interface supported.
  • Configurable data width: 8/16/32-bit
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Supports both sync and async reset
  • Clearly de-marked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The D-PHY is a complete PHY, silicon-proven at multiple foundries. The D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI), Display Serial Interface (DSI) and Unified Protocol (UniPro) using the PHY Protocol Interface (PPI). MIPI D_PHY adheres to MIPI D-PHY Specification. The MIPI D-PHY along with MIPI CSI Transmitter or CSI Receiver or DSI Host or DSI Slave provides a complete solution for encoding or decoding MIPI data.

Features

  • Compliant with MIPI D-PHY Spec v0.9
  • Programmable 1, 2 or 4 Data Lane Configuration.
  • Supports High-Speed and Low-Power modes.
  • Operate in continuous and non-continuous clock modes.
  • Data Rate: 800 Mbps per lane on silicon (Spec mentions a max of 500 Mbps per lane) in HighSpeed mode and 10Mbps in Low-Power mode.
  • Benefits

  • Highly modular design
  • Fully synchronous design
  • Active low Asynchronous reset
  • Applications

  • Verilog HDL
  • FPGA: Xilinx ISE on Virtex 5
  • Modelsim
  • Deliverables

  • RTL code
  • Detailed design document
  • Verification environment
  • Test cases
  • Synthesis environment/scripts
  • Tech Specs

  • MIPI D Phy

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The MIPI Camera Serial Interface 3 (CSI-3) is an interface between a Camera and a host processor baseband application engine. This interface, defined by MIPI Alliance, uses Unipro and MPHY for Link and PHY layers respectively. CSI-3 Host is the command decoding and pixel encoding logic between the Camera and UniPro.
GDA's CSI-3 Device IP supports two C-Ports for pixel data and one C-Port for attribute transfer. In the CSI-3 Device, the pixel data from Camera is subsequently processed before being sent upstream to UniPro. The control flow, being opposite to data flow, is initiated by the application processor, to configure UniPro, and MPHYs downstream in both Host and Device sides, and also CSI-3 Device. The GDA MIPI CSI-3 Device along with GDA MIPI UniPro, MPHY and GDA MIPI CSI-3 Host provide a complete solution for a camera application.

Features

  • Compliant with MIPI CSI-3 Spec v1.0
  • 1 C-port for CPC and 2 C-ports for Pixel/Embedded Data
  • CPC GET/SET/Notify/Response PDU Supported.
  • Mandatory Gettable/settable properties of all attributes.
  • End-to-end Support for CPC Packets.
  • Round Robin arbitration for multiple VCIDs.
  • TX Buffer Overflow Management
  • Preemptive frame handling
  • Embedded data during Vertical Blanking period supported
  • 2 source pixel data interleaving
  • Benefits

  • FPGA Validation
  • Highly Modular and Scalable Design
  • Active Low Asynchronous Reset
  • Deliverables

  • RTL Code
  • Verification Environments
  • Test suites
  • Synthesis Environment and Scripts
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The DigRF - Version 4 (DigRF v4) interface is a high-speed serial interface technology with high bandwidth capabilities, which was developed specifically for a wide range of emerging mobile applications.
DigRF provides the mobile industry a standard, high speed interface for mobile communication involving various technologies like 2G,3G and other LTE standards.
The DigRF v4 implementation is intended for galvanic point-to-point connections consisting of a single, integrated Link between a handset Baseband IC (BBIC) and a radio transceiver (RFIC). The Base-band IC acts as the master to initiate the commands and data transfer to be sent out from the Antenna. The BBIC sets the desired operating configuration. It is also responsible for enabling the RFIC and to send the correct data/configuration. The Radio transceiver IC acts as slave to receive the commands and data from BBIC. It is configured by BBIC with necessary settings. RFIC sends the data and control information to antenna Interface.
MPHY acts as a communication medium between the BBIC and the RFIC. This layer receives/transmits data serially. It is expandable up to 4 data lanes which will increase the data transfer speed between BBIC and RFIC.

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The UFS is a simple, high performance, serial interface used in mobile systems as a mechanism to communicate between host processor and mass storage devices like Flash and other non-volatile memories. This communication is achieved using a UFS Host and UFS Device, using MIPI UniPro and MPHY as Link and PHY layers respectively. UFS Device UTP Layer does the function of encoding and decoding UPIUs and forwarding of SCSI commands to the SCSI command decoder. The UFS Host & Device works perfectly with our MIPI UniPro and GDA Partner's MPHY. With this, we provide the complete solution including software.

Features

  • Compliant with UFS Spec v1.1
  • AXI3 and AHB Support
  • All UPIU Processing
  • Datain, Dataout, Command, Response, RTT & Query
  • Complete control of UIC Layer by UFS Host
  • Error Reporting and Handling Supported
  • Priority arbitration between command, query and task management UPIUs and Indexed based processing within Command and Query UPIUs.
  • Supports 32 UTP Transfer request descriptors and 8 UTP Task Management Descriptors for UFS host
  • 2 C-ports
  • Up to 8 LUNs configurable
  • Benefits

  • FPGA Validation
  • Highly Modular and Scalable Design
  • Active Low Asynchronous Reset
  • Deliverables

  • RTL Code
  • Verification Environments
  • Test suites
  • Synthesis Environment and Scripts
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The MIPI MDDI Unified Solution is compliant with the MIPI Alliance Standard for D-PHY version 1.0 and the VESA Mobile Display Digital Interface Version 1.2 specification.

It consists of 4 lanes, 1 Clock/Strobe lane, 1 bidirectional data lane and 2 unidirectional data lanes, which makes it suitable for display interface applications.

The MDDI and MIPI blocks share the same signal and supply pins. The on-chip receive termination can be used for both MDDI and MIPI. The termination resistors can be calibrated to minimize variations. Once the Display module is qualified it can be used for both MIPI and MDDI resulting in faster time to market and in area and cost savings.

Features

  • Configurable as MIPI Slave or MDDI Client
  • Complies with MIPI Alliance Specification for D-PHY V1.0 and VESA MDDI V1.2
  • Consists of 1 Clock/Strobe lane, 1 bidirectional data lane and 2 unidirectional data lanes
  • Supports both high speed and low-power modes
  • Operates up to 800 Mbps/lane in high speed mode
  • De-Serializers included
  • Optimized for minimal power dissipation & footprint
  • Programmable integrated receive termination
  • Programmable reverse MDDI TX amplitude and CMV(Common Mode Voltage)
  • Built-in testability to enable for full speed production test
  • Silicon Proven in multiple Fabs/Nodes
  • Deliverables

  • RTL code
  • Detailed design document
  • Verification environment
  • Test cases
  • Synthesis environment/script

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The PCIe/SATA combo PHY implements the lower (physical) layer protocols (of SATA,PCI Express) providing data transmission and reception over a dual differential pair cable. The TX (transmit) and RX (receive) serial channels operate plesiochronously (NRZ). The macrocell can be used in Host or Device applications.

Features

  • Serial transceiver (PHYsical layer)
  • Serializer and Deserializer
  • Direct support for 6.0 Gbit/s SATA rates and 5.0 Gbit/s PCI Express
  • Backward compatible with 1.5, 3.0 and 2.5 Gbit/s rates
  • 20-bit parallel interface
  • Comma detect to provide word alignment of incoming serial stream
  • SSC modulation
  • Requires DC-balanced encoding scheme
  • Integrated impedance adaptation to transmission line characteristics
  • OOB signaling
  • JTAG test access port allows:
  • Internal loop-back for self-test
  • Random pattern auto-test
  • 65 nm CMOS technology
  • 1.2 V and 2.5 V power supply
  • High-performance PLL
  • Programmable TX buffer pre-emphasis, slew-rate and amplitude.
  • Dedicated TX buffer regulator giving:
  • improved transmit buffer noise immunity
  • improved buffer level stability
  • Integrated BIST allows:
  • Self test of the macrocell in loop back mode at Gigabit rate on production testers
  • Self test of the macrocell at system level, either in internal/external loop back mode or between different chips in transmission mode
  • Applications

  • SATA (i, m)
  • PCI Express
  • Transmission schemes encoding octets as 10-
  • bit code groups to form a DC-balanced stream
  • High performance backplane interconnect
  • Deliverables

  • RF including schematics, database and test bench
  • RTL source code
  • GDS II production licenses
  • Grey Box (Analog/RF GDSII, Digital, FW, SW as source code)
  • White Box (Source Code of complete design data base)
  • SW source code

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

SATA AHCI controller is a highly configurable core and implements the SATA Host bus adaptor that can be interfaced with standard third party SATA PHY. The core leverages design expertise from its high speed interconnect family of IP's including USB 3.0, SSIC, Unipro, UFS.
The SATA AHCI Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings when used in laptop and power-sensitive embedded systems.
The controller exposes a high performance system interface such as AXI/PCIe for use in servers and high end storage networks or an area optimized system interface such as AHB for use in embedded systems.
The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. T2M allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally.
SATA3.0 Controller

Features

  • Compliant with SATA 3.0 and AHCI 1.3 Standards
  • Supports all generation of SATA Devices – Gen 1, Gen 2, Gen3 (1.5, 3.0 and 6.0 Gbps data rates, respectively)
  • Support DMA and PIO protocols
  • Supports all HBA Capabilities
  • Supports Native command Queueing
  • Supports Hot-plug feature.
  • 32 Command Slots per port
  • Supports Command Completion Coalescing
  • Aggressive Link Power Management
  • Auto-generating Partial-Slumber state transitions when no commands available for processing.
  • Command and FIS based switching
  • Fully programmable FIS content.
  • Includes support for BIOS/OS Handoff
  • Supports Multiple DRQ block data transfers for PIO command protocol
  • Supports up to 32 ports
  • Datapath Width : 32/64 bits; PHY Interface : 8/16/32-bit
  • Master Interface for system access : AHB/AXI
  • Slave Interface for Register access : AHB/PBUS
  • Configurable FIFOs
  • Support for port multipliers.
  • Benefits

  • Highly modular and configurable design
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Multiple loop backs for debug
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

CPCI-X is a PCI-X compliant design scoped to provide a system interface to any networking application involving streaming data transfers. It basically focuses on the transfer of large chunks of data between the DMA unit of backend and the host memory adhering to PCI-X protocol (Rev 1.0) which is downward compatible with PCI protocol(Rev 2.2) and also on configuring the backend registers through memory accesses. The core provides a DMA arbitrator (optimized for two DMA controllers) and the initiatortarget pair to handle these transactions as per the PCI-X(Rev 1.0) protocol.

Features

  • Fully compliant with PCI-X protocol (Rev 1.0)
  • Posting for outbound memory writes
  • Basic power management supported in PCI-X mode
  • MSI capability
  • 64/32 addressing capability
  • 64/32 data transfer capability
  • Medium decode time supported for target
  • Flexible master-target interface that can be customized for varied data streaming applications
  • Fully synchronous design
  • PCI-X bus operation up to 133MHz
  • Good debugging support for erroneous transactions.
  • Applications

  • Good debugging support for erroneous transactions.
  • Highly modular design
  • Fully synchronous, technology-independent design
  • 64-bit wide internal data path
  • Clearly demarked clock domains
  • Deliverables

  • RTLcode
  • Detailed design document
  • Verification environment
  • Test cases
  • Synthesis environment guide
  • User Guide
  • Verification guide
  • Synthesis Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

Our Display Port is VESA DP1.1a, DP1.2 and eDP compliant with four main lanes and an auxiliary channel The DP transmitter acceptsDP1.1a HBR (2.7Gbps) and RBR (1.62Gbps) data rates; it can also support turbo mode (3.24Gbps) and HBRII (5.4Gbps) of DP1.2 standard. Signals are sampled from 1/2/4-lane double-wide DP stream data.
IP is composed of DP 1.2 core and its Physical Layer, in 65nm, 40nmLP and 28nmLP.

Features

  • DP SST and MST compliant
  • Support video format of RGB, YCbCr 4:4:4/4:2:2
  • Deep color up to 16bit per component, H Sync, V Sync, Field ID (Interlaced modes) and DE.
  • Support dual bus video
  • Audio up to 4ch I2S
  • Support HDCP data decryption
  • Support DP 1.2 side band and GTC messages
  • Support DP 1.2 3D and SDP nesting
  • To facilitate lower test cost and improve test coverage, a loopback test is provided to check for the functionality of the transmitter in different speed modes
  • Deliverables

  • RTL Code
  • Verification Environment
  • User Documents & Guide

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

  • T2M offers best in class highly configurable 16Gbps SerDes PHY, targeted for both enterprise and client application, complaint to PCie 4.0 specification 0.3. The PHY IP is designed to support a wide range of applications and can provides maximum throughput. The customer has a choice to customize it for lower data rates and upto 4 lanes configuration. This SerDes PHY integrated with partner company PCIe 4.0 controller to offer an complete integrated PCIe 4.0 hard IP.
  • This SerDes supports wide range of industry Standards including PCIe 4.0, USB 3.1, XFI/SFI, JESD204B etc.
  • PCIe_GEN4.0_PHY is multi-standard, high performance, low power, Single-Lane PCI Express Electrical PHY that can handle high level PCI Express protocol and its signalling needs. It is compliant to PCI Express Gen 4.0 base specifications 0.3 by PCI-SIG team and has features like clocking and clock & Data recovering, Serialization and De-Sterilization of Data, 128/130b 8/10b, data coding, Receiver detection and support high performance to Media Access Control layer device.
  • T2M's PCIe GEN 4.0 PHY uses 32/16bit Data PIPE interface. Its PIPE interface is a super set of PIPE interface for the PCI Express (PIPE) 4.0 specifications. It also supports latest lower power management’s states like L0s, L1, L1-sub-states and L2. PHY Gen 4.0 PHY IP is available in TSMC 28nm HPC/HPC+ process .
  • Available SerDes PHY for the 10G/5G/2.5/10/16 Gbps
  • Foundry 28,55 and 65nm

Features

  • Compliments to PCI Express base specification 4.0 and backward compatibility
  • QUAD PCI Express 16/8/5/2.5Gbps per LANE and available in QUAD configuration
  • Lowest latency in the Industry and Adaptive CTLE and 3 tap DEF receive equalization
  • Configurable parallel data width of 8,16,32
  • Single Supply voltage of 0.9V, Temp -40 to 125 deg C
  • Tight control over termination resistor ( ~ 50 ohm) with on chip calibration
  • Input reference clock of 100MHz to support 2.5G/5G/8G/16G data rates
  • Support AC/DC coupled modes, Programmable VGA and Peak amp to support different cable applications
  • Separate Amplitude path for Eye-diagram monitoring/DFE tap calibration/offset calibration
  • CDR logic for better data alignment and locking , 3 taps TX equalization ( pre, main, post cursor ) , Programmable pre-emphasis
  • Applications

  • Storage Area Networks (SAN)
  • Solid State Drives (SSD)
  • Networking Interface card
  • Server
  • Repeater
  • Deliverables

  • Detailed specification of PCIe 16G PHY with All log files and signoff checklist agreed by customers
  • Integration Guidelines ( Interface details, layout guidelines, power requirements)
  • GDSII layout and Mapping file with LEF Abstract (Top level pin details, blockages and Boundary details)
  • LVS compatible netlist for the LVS clean
  • Verilog-A Model and IBIS mode ( optional)

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

T2M offers best in class highly configurable PCIe 3.0 PHY, targeted for both enterprise and client application, complaint to PCie 3.0 specification and ECN 1.0a. The PHY IP is designed to support a wide range of applications and can provides maximum throughput through its eight lanes configuration. The customer has a choice to customize it for lower data rates (Gen2) or lower number of lanes. It also supports L1 sub states L1.1 and L1.2 which enables its seamless integration in power constraint applications, while keeping low in the silicon area.
T2M offers an option of complete integrated PCIe 3.0 hard IP including partner company controller and standalone PHY IP.
  • Available PCI PHY
  • PCIe 3.0 8 & 16Gbps
  • Foundry - 65,55,28nm

Features

  • PCIe 3.0 PHY with backward compatibility
  • Supports L0-L2 power states and L1.1 and L1.2 substates
  • Configurable parallel data width 8,16,32 Bits, OCTAL ( 8Tx, 8Rx) QUAD ( 4 TX and 4RX ), Single Lane Configuration (1 Tx, 1Rx)
  • Support Signal loss & receiver detection with CTLE and 3 Tap DFE receiver equalization
  • Support upto 20 inch SL channel
  • Optimized Metal Stakes for Lower NRE expense ( 6020+LB )
  • 1.0V supply to support -40 to 125 Deg.C
  • CDR logic for better data alignment and locking , Integrated PCS Layer; compliant to PIPE specification
  • Applications

  • Storage Area Networks (SAN)
  • Solid State Drives (SSD)
  • Networking Interface card
  • Server
  • Repeater
  • Deliverables

  • White Box Design Data Base
  • GDSII ported to required process node
  • Physical Design scripts - Synopsys synthesis
  • Datasheet, Characterization Report
  • Comprehensive documentation and Support

Please fill in the form below

T2M's range of high quality pre-verified, analog/mixed-signal, RF, Digital and SW system solutions, are used as critical building blocks of communications, consumer and computer products including IoT, Wearables, cellular, tablet, M2M, RCU, set-top boxes, TVs, DVD players and PC chipsets. IPs can be modified to meet the customer's specific requirement be it fab/node porting or proprietary features.