USB 3.1 Host Controller IP
USB 3.1 Host controller is a highly configurable core and implements the USB 3.1 Host functionality that can be interfaced with third party USB 3.1 PHY’s. USB3.1 Host controller core is part of USB3.0 family of cores named “Pravega”.
The Pravega Host Controller core is architected with an optional high performance DMA engine based on xHCI specification. The core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.
The Pravega Host Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications.
The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.
The Controller also has a dedicated PHY Type-C connector Interface for identifying Type-C specific features such as cable orientation, ID function based on Configuration data channel etc.
- Compliant with xHCI and USB3.1 Specification Rev1.0
- Implements Phy Logical/ Link / Protocol Layers.
- Asynchronous clocking between Host Controller and Application logic
- Supports Aggressive Low Power Management
- Configurable system clock frequency
- Optional Support for simultaneous Multiple IN transfers.
- Configurable PIPE Interface: 8, 16, 32 bit.
- Flexible User Application Logic
- Supports Type2 Header Buffers
- Supports SCD/LBPM LFPS Messages
- Simple Register Interface for internal Register Access.
- Optional support for Type-C connectors
- Support for various Hardware and Software Configurability regarding Core characteristics.
- Support Data, Video and Switch function
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Extensive clock gating support
- Multiple Power Well Support
- Software control for key features
- Multiple loop backs for debug
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shellz