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SoC White Box IPs

xP70-RISC IP-IoT

OverviewFeaturesRequest Datasheet

Description

The xP70 RISC processor is a configurable 32-bit or 16/32/48-bit scale able RISC core, developed and used widely by a Tier 1 semiconductor company, ideal for Internet of Things (IoT), Wearables, Sensors, BLE, BT, ZigBee, WiFi and other very low power real time applications.

Data Streaming Offload processor with high data latency can implement on the fly Audio/Video formatting.

The xP70 CISC core is very real time efficient with highly optimized silicon area and power.

The core is scalable and can be configured to run in groups, the smallest implementation is 40 KGate. The core can run up to 450MHz in 65nm while consuming less than 0.05 mW/MHz.

A programmable extension capability enables repetitive routines to be executed in HW through a single instruction call, providing >150 times acceleration for real Application , Data Streaming Offload processor with high data latency can implement on the fly Audio/Video formatting.

The xP70 CISC core is very real time efficient with highly optimized silicon area and power.

The core is royalty free and makes an excellent alternative to a Cortex M0, 1, 3, 4 class processor.

xP70 Application Specific MultiProcessor -

  • ASMP goal, similarly to STxP70 mono-processor, is to provide a technology for developing flexible and efficient embedded accelerator.
  • ASMP mixes processor specialization with parallelization to offer high level performance.
  • Take benefit of STxP70 specialization to get powerful elementary processing core
  • Get another performance step through coarser grain parallelization
  • Be power consumption aware thanks to fine grain idle mode management
  • Configurability and scalability are two major driving factors
  • ASMP programming models and execution vehicles
  • Offer simple, easy way for programming ASMP: FreeRTOS and well known OpenMP programming model
  • Supported by three execution platforms (TLM, GePOP and FPGA boards)

xP70 V4 Extensions Library

  • CRCx Cryptography
  • FPx Floating Point Unit
  • MP1x Media Processing Unit
  • DIVS - Division & SQRT Unit
  • HWIx-Streaming interface
  • VECx-Video/Imaging Vectorial
  • VECL-Video/Imaging Vectorial
  • M2x-MoCA2 Control
  • Tx-Transport Extension
  • FDx Face detection
  • D6Mx Docsis Multicontext
  • VCR Vector Complex/Real
  • DIVS - Division & SQRT Unit
xp70

Features

  • Configurable 32-bit or 16/32/48-bit RISC core
  • Low-cost control and real-time applications
  • DSP applications
  • Algorithm acceleration
  • Highly configurable core
  • Native extensions: FPx, DIVS, MP1x
  • Program and data caches
  • Memory protection unit
  • Intelligent DMA called Streamer
  • xP70 Professional toolset (mono & multiprocessor)
  • Applications

  • Low-cost Control & real-time applications
  • DSP applications
  • HDTV
  • Set Top Box Chipsets
  • Digital Still Camera
  • Cellular Phone
  • Deliverables

  • VHDL source code
  • Free RTOS Mono and multi processor
  • Custom extension development

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OverviewFeaturesRequest Datasheet

Description

The D32PRO is royalty-free silicon proven, high performance soft core of a single-chip 32-bit em-bedded controller, with Floating Point Coproces-sor. Thanks to its increased code density, the D32PRO meets the power and size requirements of new connected devices. That's why both power and performance of this IP Core predestine it as a real alternative for ARM Cortex M0/M0+/M1/M3 in the deeply embedded market and especially for emerging market of connected devices (IoT). Re-sponding to continuing demands for less power drain in system-on-chip (SoC) designs, DCD has developed an instruction set aimed at reducing the size of system's instruction memory.
The D32PRO is aimed at low-power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Low Energy. Nevertheless the core is perfect for embedded systems that require greater computational per-formance and system complexity by supporting dual- and multi-core systems as well as improved code density. DCD's IP Core is fully customizable - it is delivered in the exact configuration to meet customer's requirements.
The D32PRO is offered with great variety of peripherals like USB, SPI, LCD, HDLC, UART, Ethernet MAC, CAN, LIN, RTC and many more – ready to be implemented with the CPU. The D32PRO is delivered with fully automat-ed test bench and complete set of tests, allowing easy package validation at each stage of SoC design.
d32pro

Features

  • ASIC Silicon proven architecture
  • Performance up to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz
  • Small footprint starting at 10.6k / 6.7k ASIC gates
  • Dynamic power below 7 uW/MHz in 90nm
  • Very high clock frequency up to 1 GHz in modern ASIC technologies
  • Configurable 32-bit Harvard architecture
  • Fifteen 32-bit general Purpose registers
  • Up to 256 MB of Code Space with encrypted bootloader
  • Up to 256 MB of Data Space
  • Built-in configurable Floating Point co-processor using dedicated instructions
  • Configurable 32-bit hardware multiplier
  • Configurable 32-bit hardware divider
  • Configurable 32-bit hardware shifter
  • Low power consumption by Advanced Power Management Unit
  • Advanced Power management mode
  • Switchback feature
  • Stop mode
  • Deliverables

  • VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros Tests with reference responses
  • Technical documentation Installation notes HDL core specification Datasheet
  • Synthesis scripts Example application Technical support

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OverviewFeaturesRequest Datasheet

Description

The DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The core is fully configurable and allows selection of its features and peripherals, to create a dedicated system. It has been designed with a special concern of performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit. This product is built based on 14 years of know-how, with triumphant 8051 architectures. The DQ80251 soft core is 100% binary-compatible with industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. There are two working modes of the DQ80251: BINARY (where the original 80C51 compiled code is executed) and SOURCE (a native 80C251 mode, using all DQ80251 performance). The DQ80251 has a built-in, configurable DoCD-JTAG on chip debugger, supporting Keil DK251 and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs 66 times faster than the original 80C51 and 5.5 times faster, than the original 80C251 at the same frequency. This performance can be also exploited to great advantage in low power applications, where the core can be clocked over fifty times slower than the original implementation, with no performance penalty. Additionally, the compiled code size for the SOURCE mode is about 2 times smaller comparing to the identical standard 8051 code, due to higher efficiency of DQ80251 instructions. The DQ80251 is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.

Each of our 80251 cores has a built-in support for Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).

Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD's on-chip Debugger. Performance Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

DQ80251 core area and performance in ASIC devices - results given for working system with connected CODE and DATA memories. All CPU features and Peripherals have been included. DoCD JTAG debugger increases core size by approximately 2900 gates.

80251

Features

  • 100% binary compatible with industry standard 80C251, implementing BINARY and SOURCE modes
  • Single clock period per most of instructions
  • Quad-Pipelined architecture enables to run 66 times faster than the original 80C51 and 5.5 times faster, than the 80C251 at the same frequency
  • Up to 61.8 VAX MIPS at 100 MHz
  • Up to 8M bytes of Program Memory
  • Up to 32k bytes of internal (on-chip) Data Memory
  • Up to 8M bytes of external (off-chip) Data Memory
  • Up to 16 MB of total memory space for CODE and DATA
  • 32k bytes of extended stack space
  • User programmable Program Memory Wait States solution - for wide range of memories' speed
  • User programmable Extended Data Memory Wait States solution - for wide range of memories' speed
  • De-multiplexed Address/Data bus, to allow easy connection to memory
  • Full Program Memory writes
  • Interface for additional Special Function Registers
  • Fully synthesizable
  • Static synchronous design
  • No internal tri-states
  • Scan test ready

Deliverables

  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support

Tech Specs

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OverviewFeaturesRequest Datasheet

Description

The D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, its code is compatible with the MC68008, upward code compatible with MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. Our efficient IP Core has an improved instructions set, which allows to execute the program with higher performance, than a standard 68000 core.

The D68000 is delivered with fully automated test-bench and complete set of tests, which allow easy package validation at each stage of SoC design flow.

A special testing platform has been built to run D68000 with uCLinux Operating System

68000-ip

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below

1385216237_68000-size

Features

  • Software compatible with 68000 industry standard
  • MULS, MULU take 28 clock periods
  • DIVS, DIVU take 28 clock periods
  • Optimized shifts and rotations
  • Idle cycles removed to improve performance
  • Shorter effective address calculation time
  • Bus cycle timings identical to 68000
  • 32 bit data and address registers
  • 14 addressing modes:
    • Direct:
      • Data register direct
      • Address register direct
    • Indirect:
      • Register indirect
      • Postincrement register indirect
      • Predecrement register indirect
      • Register indirect with offset
      • Indexed register indirect with offset
    • PC relative:
      • Relative with offset
      • Relative with index and offset
    • Absolute data:
      • Absolute short
      • Absolute long
    • Immediate data:
      • Immediate
      • Quick immediate
      • Implied
  • 5 data types supported:
    • bits
    • BCD
    • bytes, words and long words
  • Arithmetic Logic Unit includes:
    • 8,16,32-bit arithmetic & logical operations
    • 16x16 bit signed and unsigned multiplication
    • 32/16 bit signed and unsigned division
    • Boolean operations
  • Interrupt controller:
    • 7 priority levels interrupt controller
    • Unlimited number of virtual interrupt sources
    • Vectored and auto-vectored modes
  • Memory interface includes:
    • Up to 4 GB of address space
    • 16-bit data bus
    • Asynchronous bus control
  • M6800 family synchronous interface
    • 3- and 2- wire bus arbitration
    • Supervisor and user modes
  • Fully synthesizable
  • Static synchronous design
  • Deliverables

  • Source code:
    • VHDL Source Code or/and 
    • VERILOG Source Code or/and 
    • Encrypted, or plain text EDIF 
  • VHDL & VERILOG test bench environment 
    • Active-HDL automatic simulation macros 
    • ModelSim automatic simulation macros 
    • Tests with reference responses 
  • Technical documentation 
    • Installation notes 
    • HDL core specification 
    • Datasheet 
  • Synthesis scripts 
  • Example application 
  • Technical support 
    • IP Core implementation support 
    • 3 months maintenance 
    • Delivery the IP Core updates, minor and major versions changes 
    • Delivery the documentation updates 
    • Phone & email support 

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OverviewFeaturesRequest Datasheet

Description

The DF6811 is an advanced 8-bit MCU IP Core, with highly sophisticated, on-chip peripheral capabilities. DF6811 soft core is binary-compatible with the industry standard Motorola 68HC11 8-bit microcontroller. It has an improved FAST architecture, that is approximately 4 times faster, compared to original implementation. In the standard configuration, the core has integrated on chip, major peripheral functions.
The Core can be provided in configurations, that match the following:
  • 68HC11F/K
  • 68HC08/05/11E/11F/K
  • MC6803/02/09/03/02
An asynchronous serial communications interface (SCI) and separate synchronous serial peripheral interface (SPI), are included. The main 16-bit, free-running timer system has three input capture and five outputcompare lines and a real-time interrupt function.
An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self-monitoring on-chip circuitry is included, to protect DF6811E from system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non maskable interrupt if illegal opcode is detected.
Two software-controlled power-saving modes - WAIT and STOP are available, to conserve additional power. These modes make the DF6811E IP Core especially attractive for automotive and battery-driven applications. The DF6811E has a built-in real time hardware on-chip debugger -DoCDTM, allowing easy software debugging and easy package validation at each stage of SoC design flow.
14695970196811f
 

Features

  • FAST architecture, 4 times faster than the original implementation
  • Software compatible with industry standard 68HC11
  • 10 times faster multiplication
  • 16 times faster division
  • De-multiplexed Address/Data Bus to allow easy integration with external memories.
  • Interrupt Controller
  • Two power saving modes: STOP, WAIT
  • Fully synthesizable, static synchronous design with no internal tri-states
  • No internal reset generator or gated clock
  • Scan test ready

Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application
  • Technical support

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

The DQ8051CPU is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, designed to operate with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU. The DQ8051CPU soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. The DQ8051CPU has a built-in configurable DoCD-JTAG on chip debugger, supporting Keil µVision development platform and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs from 19.69 to 26.62 times faster than the original 80C51 at the same frequency. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times more slowly than the original implementation, with no performance penalty. The DQ8051CPU is fully customizable - it is delivered in the exact configuration to meet your requirements. There is no need to pay extra for not used features and wasted silicon.
The DQ8051CPU is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
Each of DCD's 8051 cores has a built-in support for DCD's Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. More details about DCD's on-chip debugger
8051

Features

  • software is 100% compatible with 8051 industry standard
  • Quad-Pipelined architecture enables to run 26.62 times faster, than the original 80C51 at the same frequency
  • Up to 25.053 VAX MIPS at 100 MHz
  • 24 times faster multiplication
  • 12 times faster division
  • 2 Data Pointers (DPTR) - for faster memory blocks copying
    • Advanced INC & DEC modes
    • Auto-switch of current DPTR
  • Up to 256 bytes of internal (on-chip) Data Memory - IDM
  • Up to 64k bytes of Program Memory
  • Up to 16 MB of external (off-chip) Data Memory - XDM
    • Synchronous interface - for up to 64K bytes of (on-chip) fast external Data Memory - (SXDM)
  • User programmable Program Memory Wait States solution -  for wide range of memories' speed
  • User programmable External Data Memory Wait States solution - for wide range of memories' speed
  • De-multiplexed Address/Data bus - to allow easy memory connection
  • Interface for additional Special Function Registers
  • Fully synthesizable
  • Static synchronous design
  • No internal tri-states
  • Scan test ready

Benefits

  • DQ8051CPU core area and performance in ASIC devices -results given for working system with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals have been included. DoCD JTAG debugger increases core size by approximately 2 100 gates.
  • DQ8051CPU core area and performance in XILINX devices -results given for working system   with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals have been included.
  • DQ8051CPU core area and performance in ALTERA devices -results given for working system   with two DPTRs and connected 256B IDM, 8kB CODE and 2kB SXDM memories. All CPU features and Peripherals have been included.

Deliverables

Source code:

  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros 
  • ModelSim automatic simulation macros 
  • Tests with reference responses 
  • Technical documentation 
  • Installation notes 
  • HDL core specification 
  • Datasheet 
  • Synthesis scripts 
  • Example application 
  • Technical support 
  • IP Core implementation support 
  • 3 months maintenance 
  • Delivery the IP Core updates, minor and major versions changes 
  • Delivery the documentation updates 
  • Phone & email support 

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OverviewFeaturesRequest Datasheet

Description

The DZ80 is an advanced, 8-bit microprocessor, with 208 bits of user-accessible registers. It is composed of six general purpose registers, which can be used individually, as either 8-bit or 16-bit register pairs. Additionally, DZ80 supports two sets of accumulator and flag registers. The DZ80 contains also Stack Pointer, program Counter, two index registers, a REFRESH register and an INTERRUPT register. All output signals are fully decoded and timed, to control standard memory or peripheral circuits. The DZ80 is supported by a wide range of peripherals.
DZ80 is fully customizable - it is delivered in the exact configuration, to meet user's requirements. There is no need to pay extra, for unused features and wasted silicon.

Features

  • Fully compatible with Z80 industry standard
  • Fully synthesizable, static synchronous de-sign with no internal tri-states
  • No internal reset generator or gated clock
  • Scan test ready
  • Technology independent HDL source code
  • Core can be fully customized
  • Benefits

  • ONE GLOBAL SYSTEM CLOCK
  • SYNCHRONOUS RESET
  • ALL ASYNCHRONOUS INPUT SIGNALS ARE SYNCHRONIZED
  • BEFORE INTERNAL USE
  • ALL LATHES IMPLEMENTED IN ORIGINAL Z80 MICRO-CONTROLLER ARE REPLACED BY EQUIVALENT FLI-FLOPS.
  • Deliverables

  • Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • Encrypted, or plain text EDIF
  • VHDL & VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet

  • Synthesis scripts
  • Example application
  • Technical support
  • IP Core implementation support
  • 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Phone & email support

Please fill in the form below

OverviewFeaturesRequest Datasheet

Description

Spiking neural networks implemented with SNAP core operate in parallel, making them significantly faster than software neural networks running on Central Processing Units (CPUs) or Graphics Processing Units (GPUs). SNAP is more energy efficient, enabling SNN to be integrated into portable devices for local processing of sensor data. SNAP based neural networks can respond in real time with low latency, regardless of the neural network size. SNAP implements learning rules in hardware, enabling Autonomous Features Extraction (AFE) directly from input data without need for any software processing .
SNAP based neuromorphic chips can be used in nearly any embedded systems that requires pattern recognition or AFE locally without having to go to cloud based computations. Such systems represent a massive and unlimited potential market, with applications in Smartphones, Internet of Things (IoT), machine to machine (M2M), robotics, gaming, driverless vehicles, drones and air transportation among others.
snap

Features

  • Neural Network updates at 1MHz
  • Fully parallel computation
  • Real time pattern recognition
  • Input from DVS camera
  • Unsupervised feature learning
  • Spike Timing Dependent Plasticity
  • Library of learned features
  • Labeled output (vehicles counts)
  • Benefits

  • Fast, independent of size
  • Highly energy efficient
  • Real time response
  • Unsupervised Learning
  • Actionable data
  • Customizable Network
  • Applications

  • Surveillance and security cameras
  • Smartphones
  • Internet of Things (IoT)
  • Machine to machine (M2M)
  • Robotics, Gaming
  • Driverless Vehicles
  • Drones and Air Transportation
  • Deliverables

  • SNAP based Spiking Neural Network RTLv
  • Configurable Neuron and Synapses
  • Configurable Learning rules
  • Configurable synaptic connectivity
  • Proprietary spike communication protocol
  • Direct connection to sensory inputs
  • Creation of libraries of learned behaviors
  • SNAP Models Integrated with Neural Network Simulators like NENGO*
  • Design services for SNAP customization
  • Hardware emulation in FPGA
  • Configuration management tools

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T2M's range of high quality pre-verified, analog/mixed-signal, RF, Digital and SW system solutions, are used as critical building blocks of communications, consumer and computer products including IoT, Wearables, cellular, tablet, M2M, RCU, set-top boxes, TVs, DVD players and PC chipsets. IPs can be modified to meet the customer's specific requirement be it fab/node porting or proprietary features.