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SoC White Box IPs

HDMI V1.3 Rx PHY IP

OverviewFeaturesRequest Datasheet

Description

HDMI receiver PHY (Physical layer) IP is single-port core which is fully compliant with HDMI 1.3a specification. This HDMI Rx PHY supports from 25MHz to 225MHz TMDS clock, and offers a simple implementation for system LSI for consumer electronics like HDTV. The HDMI Rx PHY performs most efficiently with HMDI receiver link IP core.

It is Silicon Proven in many Fab/Nodes including: 130/90/65/55/45/40nm.

Features

  • HDMI version 1.3a compliant receiver
  • Supports DTV from 480i to 1080i/p HD resolution
  • Supports 24bit, 30bit and 36bit color depth per pixel
  • Integrated cable terminator
  • Adaptive equalizer for cable
  • Adjustable analog characteristics
  • PLL band width
  • VCO gain
  • BGR voltage
  • Cable terminator resistance value
  • DLL digital filter characteristics
  • Integrated Audio PLL
  • 3.3V/2.5V/1.0V power supply
  • GLOBAL FOUNDRIES 65nm (C65G) proces
  • Deliverables

  • Datasheet
  • Integration guideline
  • GDSII or Phantom GDSII
  • Layer map table
  • CDL netlist for LVS
  • LEF
  • Verilog behavior model
  • Liberty timing model
  • DRC/LVS/ERC results

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T2M's range of high quality pre-verified, analog/mixed-signal, RF, Digital and SW system solutions, are used as critical building blocks of communications, consumer and computer products including IoT, Wearables, cellular, tablet, M2M, RCU, set-top boxes, TVs, DVD players and PC chipsets. IPs can be modified to meet the customer's specific requirement be it fab/node porting or proprietary features.