PHYS40 IP is a high performance SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption.

• Compatible with PCIE/USB3/SATA base Specification
• Fully compatible with PIPE3.1 interface specification
• Data rate configurable to 1.G/2.5G/3G/5G/6G for different application
• Support 16-bit or 32-bit parallel interface when encode/decode enabled
• Support 20-bit parallel interface when encode/decode bypassed
• Support flexible reference clock frequency
• Support 100MHz differential reference clock input or output (optional with SSC) in PCIE Mode
• Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
• Support programmable transmit amplitude and De-emphasis
• Support TX detect RX function in PCIE and USB3.0 Mode
• Support Beacon signal generation and detection in PCIE Mode
• Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode
• Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode
• Support L1 sub-state power management
• Support RX low latency mode in SATA operation mode
• Support Loopback BERT and Multiple Pattern BIST Mode
• ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA