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    8G Multi Protocol SerDes IP

    OverviewFeaturesRequest Datasheet

    PHYS40 IP is a high performance SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption.

    PHYS40 IP support multiple application including USB3.0 Super Speed (5GT/s), PCIE Gen1/Gen2 (2.5GT/s and 5GT/s) and SATA Gen1/Gen2/Gen3 (1.5GT/3GT/6GT). PHYS40 IP includes PMA IP with maximum 6. Gbps data rate macro that can be used in other application.
    • Compatible with PCIE/USB3/SATA base Specification
    • Fully compatible with PIPE3.1 interface specification
    • Data rate configurable to 1.G/2.5G/3G/5G/6G for different application
    • Support 16-bit or 32-bit parallel interface when encode/decode enabled
    • Support 20-bit parallel interface when encode/decode bypassed
    • Support flexible reference clock frequency
    • Support 100MHz differential reference clock input or output (optional with SSC) in PCIE Mode
    • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
    • Support programmable transmit amplitude and De-emphasis
    • Support TX detect RX function in PCIE and USB3.0 Mode
    • Support Beacon signal generation and detection in PCIE Mode
    • Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode
    • Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode
    • Support L1 sub-state power management
    • Support RX low latency mode in SATA operation mode
    • Support Loopback BERT and Multiple Pattern BIST Mode
    • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA

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