The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data are simultaneously transmitted and received. What's the most important, it's a technology independent design that can be implemented in a variety of process technologies.
The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. It can be configured as a master or a slave device, with data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock.
The DSPI automatically drive selected by SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. What's more important, error-detection logic is included to support interprocessor communications. A write collision detector indicates, when an attempt is made, to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI devices simultaneously attempts to become bus master. What does it mean for you? The DSPI is fully customizable, which means that we deliver it tailored to your configuration and requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.
- SPI Master - 8 SPI slave select lines System error detection Mode fault error Write collision error Interrupt generation
- Supports speeds up 1/4 of system clock Bit rates generated 1/4 - 1/512 of system clock. Four transfer formats supported Simple interface allows easy connection to microcontrollers
- SPI Slave operation - System error detection, Interrupt generation
- Supports speeds up 1/4 of system clock Simple interface allows easy connection to microcontrollers Four transfer formats supported
- system interface wrappers: AMBA - APB Bus, Altera Avalon Bus, Xilinx OPB Bus
- Fully synthesizable, Static synchronous design, Positive edge clocking and no internal tri-states Scan test ready
- VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF
- VHDL & VERILOG test bench environment Active-HDL automatic simulation macros
- ModelSim automatic simulation macros Tests with reference responses
- Technical documentation Installation notes HDL core specification Datasheet
- Synthesis scripts Example application Technical support