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DDR3L/DDR4 Combo PHY

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This DDR PHY IP supports DR3L/ DDR4/ LPDDR4, provides low latency, and enables up to 1866Mbps throughput. The PHY IP is silicon proven and designed for ease of integration and faster time-to-market.
Supported DRAM type: DDR3L/DDR4/LPDDR4 Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps Interface: SSTL135/POD12/LVSTL Data path width scales in 32-bit increment Four modules for flexible configuration: CA/DQ_X16/DQ_X8/ZQ Programmable output impedance (DS) Programmable on-die termination (ODT) Core power:0.9V, I/O power (VDDQ):1.5V/1.35V/1.2V, RX power:1.8V ESD: 2KV/HBM, 200V/MM, 500V/CDM Support ZQ calibration Support 8 ranks Support write-leveling, CBT Support PHY internal VREFDQ auto decision Per-bit deskew in read and write datapath Supported metal scheme: 1P7M_1C
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