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The DDR PHY IP supports DDR3L/DDR4/LPDDR4, provides low latency, and enables up to 3200Mbps throughput. The PHY IP is silicon proven and designed for ease of integration and faster time-to market.
  • Supported DRAM type: DDR3L/DDR4/LPDDR4
  • Maximum controller clock frequency of 800MHz resulting in maximum DRAM data rate of 3200Mbps Interface:
  • SSTL135/POD12/LVSTL Data path width scales in 8-bit increment Four module for flexible configuration:
  • Programmable output impedance(DS) Programmable on-die termination(ODT)
  • Core power:0.8V
  • ESD : 2KV/HBM, 200V/MM, 500V/CDM
  • Support ZQ calibration
  • Support 4 ranks by each CA module
  • Support write-leveling, CBT Support PHY internal VREFDQ auto decision
  • Per-bit deskew in read and write datapath
  • TSMC 12nm FFC IP9M 2xa1xd3xe2z AL=28k (ULVT/SVT) process
  • Flip-Chip
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