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    DVB S2X Modulator IP

    OverviewFeaturesRequest Datasheet

    DVB-S2x Modulator with integrated LDPC encoder has been designed specifically to address the requirements of the ETSI DVB-S2 forward-link satellite standard (EN 302 307), section-1 together with the section-2 extensions (DVB-S2X). The core can operate in CCM and VCM/ACM modes. The core provides all the necessary processing steps to modulate a single transport stream (or basebandframe) into a complex I/Q signal for input to a pair of DACs, or an interpolating DAC device such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC. The active FEC code-rate and frame-size are defined by the mod_cod and type parameters associated with each TS packet (or input-frame) and are controlled through the external mode control ports, or optionally from a control register for CCM applications. The design has been optimized to provide excellent performance in FPGA devices.

    • Fully compliant with ETSI EN 302 307-1 and ETSI EN 302 307-2.
    • Variable sample-rate interpolation provides ultra-flexible clocking strategy
    • Support for CCM, VCM and ACM modes. Compatible with Broadcast, DSNG, Interactive and Professional DVB-S2 and DVB-S2X profiles.
    • QPSK, 8-PSK, 16-APSK and 32-APSK supported.
    • 64-APSK, 128-APSK and 256-APSK supported.
    • Short (16kb) and normal (64kb) frames.
    • Frames with/without intra-frame pilots.
    • Automatic dummy-frame insertion.
    • Integrated LDPC channel coder.
    • Optional simultaneous DVB-CID modulation.
    • Configurable for either low-latency or highthroughput encoding.
    • Extension core available for SPI/ASI interface with integrated PCR TS re-stamping.
    • Seamless integration with Altera ASI megacore when using SPI/ASI extension core in broadcast CCM mode.
    • Optional internal IF conversion.
    • Optional noise interference source.
    • AD9857/AD9957 interface and autoprogramming support.
    • Modes that are not required may be removed with synthesis options to generate a compact, efficient design.
    • Designed for very efficient FPGA implementation without compromise to the targeting of gate array or standard cell structures.
    • Supplied as a protected bitstream or netlist (Megacore for Altera FPGA targets).

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